512Mb(x16, DDP)
DDR SDRAM
DDP 512Mbit DDR SDRAM
8M x 16bit x 4 Banks
DDR SDRAM Specification
Revision 1.0
July. 2002
This is to advise Samsung customers that in accordance with certain terms of an agreement, Samsung is prohibited from selling any DRAM
products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as mainframes, servers,
work stations or desk top personal computers (hereinafter "Prohibited Computer Use"). Applications such as mobile, including cell phones,
telecom, including televisions and display monitors, or non-desktop computer systems, including laptops, notebook computers, are,
however, permissible. "Multi-Die Plastic" is defined as two or more Dram die encapsulated within a single plastic leaded package.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev 1.0 July. 2002
512Mb(x16, DDP)
Key Features
•
Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK )
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
DDR SDRAM
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
Operating Frequencies
- B3(DDR333)
Speed @CL2
Speed @CL2.5
133MHz
166MHz
- A2(DDR266A)
133MHz
133MHz
- B0(DDR266B)
100MHz
133MHz
- A0(DDR200)
100MHz
-
*CL : Cas Latency
Functional Block Diagram
CK, CK,CAS
RAS ,WE, CS, CKE
32Mx8
32Mx8
I/O8 ~ I/O15,UDQS
I/O0 ~ I/O7,LDQS
A0-A12,BA0,BA1
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Rev 1.0 July. 2002
512Mb(x16, DDP)
Input/Output Function Description
SYMBOL
CK, CK
DDR SDRAM
TYPE
Input
DESCRIPTION
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled
during power-down and self refresh modes, providing low standby power. CKE will recognize
an LVCMOS LOW level prior to VREF being stable on power-up.
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-
ing. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on
DQ8-DQ15.
Bank Addres Inputs : BA0 and BA1 define to which bank ACTIVE, READ, WRITE or PRE-
CHARGE command is being applied.
Address Inputs : Provide the row address for ACTIVE commands, the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
Data Input/Output : Data bus
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on
DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15.
No Connect : No internal electrical connection is present.
DQ Power Supply : +2.5V
±
0.2V.
DQ Ground.
Power Supply : +2.5V
±
0.2V (device specific).
Ground.
SSTL_2 reference voltage.
CKE
Input
CS
Input
RAS, CAS , WE
LDM,(U)DM
Input
Input
BA0, BA1
A [n : 0]
Input
Input
DQ
LDQS,(U)DQS
I/O
I/O
NC
V
D D
Q
V
SS
Q
V
D D
V
SS
V
R E F
-
Supply
Supply
Supply
Supply
Input
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Rev 1.0 July. 2002
DSP and ARM Processors
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