EEWORLDEEWORLDEEWORLD

Part Number

Search

3GW576E-150N-800.00

Description
LVCMOS Output Clock Oscillator, 800MHz Nom, ROHS AND REACH COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size135KB,1 Pages
ManufacturerEuroquartz
Websitehttp://www.euroquartz.co.uk/
Environmental Compliance  
Download Datasheet Parametric View All

3GW576E-150N-800.00 Overview

LVCMOS Output Clock Oscillator, 800MHz Nom, ROHS AND REACH COMPLIANT, SMD, 6 PIN

3GW576E-150N-800.00 Parametric

Parameter NameAttribute value
Is it lead-free?Yes
Is it Rohs certified?Yes
Objectid1078112253
package instructionROHS AND REACH COMPLIANT, SMD, 6 PIN
Reach Compliance Codecompliant
Is SamacsysN
YTEOL2
Minimum control voltage0.99 V
linearity10%
Minimum supply voltage3.135 V
maximum symmetry55/45 %
Other featuresTRI-STATE
Maximum control voltage2.31 V
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate150 ppm
Maximum supply voltage3.465 V
frequency stability50%
Nominal operating frequency800 MHz
Oscillator typeLVCMOS
Output load15 pF
Nominal supply voltage3.3 V
Installation featuresSURFACE MOUNT
Number of terminals6
surface mountYES
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
physical size7.0mm x 5.0mm x 1.8mm
EURO
QUARTZ
CMOS SMD 7 x 5 x 1.8mm, 6 pad
Frequency range 200.1MHz to 800MHz
LVCMOS Output
Supply Voltage 3.3 VDC
High Q fundamental mode crystal
Low jitter multiplier circuit
DESCRIPTION
GW42 VCXOs, are packaged in an industry-standard, 4 pad, 11.4mm
x 9.6mm x 2.5mm SMD package. GW42 VCXOs incorporate a high Q
fundamental crystal and a low jitter multiplier circuit.
SPECIFICATION
Frequency Range:
Supply Voltage:
Output Logic:
Integrated Phase Jitter:
Period Jitter RMS:
Period Jitter Peak to peak:
Phase Noise:
Initial Frequency Accuracy:
Output Voltage HIGH (1):
Output Voltage LOW (0):
Pulling Range:
Temperature Stability:
Output Load:
Start-up Time:
Duty Cycle:
Rise/Fall Times:
Current Consumption
<96MHz:
>96MHz:
Linearity:
Modulation Bandwidth:
Input Impedance:
Slope Polarity:
(Transfer function)
OUTLINE & DIMENSIONS
GW576 VCXO
200.1MHz ~ 800.0MHz
200.1MHz to 800.0MHz
3.3 VDC ±5%
LVCMOS
2.6ps typical, 4.0ps maximum
(for 155.250MHz)
4.3ps typical (for 155.250MHz)
27.0ps typical (for 155.250MHz)
Tune to the nominal frequency
with Vc= 1.65 ±0.2VDC
90% Vdd minimum
10% Vdd maximum
From ±30ppm to ±150ppm
15pF
10ms maximum, 5ms typical
50% ±5% measured at 50% Vdd
1.2ns typical (15pF load)
30mA maximum (15pF load)
40mA maximum (15pF load)
10% maximum, 6% typical
25kHz minimum
2 MW minimum
Monotonic and Positive. (
Storage Temperature:
Ageing:
Enable/Disable (Tristate):
RoHS Status:
-50° to +100°C
±5ppm per year maximum
Not available (
Fully compliant
)
PHASE NOISE
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
-65dBc/Hz
-95dBc/Hz
-120dBc/Hz
-125dBc/Hz
-121dBc/Hz
-120dBc/Hz
-140dBc/Hz
FREQUENCY STABILITY
Stability Code Stability ±ppm Temp. Range
A
25
0°~+70°C
B
50
0°~+70°C
C
100
0°~+70°C
D
25
-40°~+85°C
E
50
-40°~+85°C
F
100
-40°~+85°C
If non-standard frequency stability is required
Use ‘I’ followed by stability, i.e. I20 for ±20ppm
PART NUMBER SCHEDULE
Example:
3GW576B-80N-250.00
Supply Voltage
3 = +3.3V
Series Designator
GW576
Stability over temperature range
(
)
Pullability in ±ppm
Pullability determinator
N = minimum
M = maximum
T = Typical
Frequency in MHz
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 info@euroquartz.co.uk www.euroquartz.co.uk
Solution to gedit not working in Ubuntu
Solution to gedit not working in UbuntuCategory: LINUXAfter su root, the gedit command cannot be used. As shown in the figure:jerry@jerry:~$ su rootpassword:root@jerry:/home/jerry# lsDesktop linux-2.6...
regove Linux and Android
CC2530 Download Board/Base
The project requires that the program cannot be downloaded on the product board, so it must be downloaded before welding. Therefore, I am looking for a CC2530/pin40 base. I would like to ask for advic...
DILIDILI RF/Wirelessly
About btfss and btfsc instructions
As shown in the figure, why the program can only display one number and not two numbers alternately....
windirection Microchip MCU
The clock clk is generated by the input a and b AND gate. How to program it as the clock signal of the D flip-flop in VHDL?
The clock clk is generated by the AND gate of input quantities a and b. How to program it as the clock signal of the D flip-flop in VHDL? It seems that clk cannot be defined as a variable or signal ty...
wuweiliang FPGA/CPLD
Rail pressure sensor
Have you ever made this product? Please share your experience....
zhaochong110 Sensor

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1818  1401  2683  1316  1318  37  29  55  27  19 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号