Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51AG128
Rev. 5, 6/2010
MCF51AG128
MCF51AG128 ColdFire
Microcontroller
Covers: MCF51AG128 and
MCF51AG96
The MCF51AG128 is a member of the ColdFire
®
family of
32-bit variable-length reduced instruction set (RISC)
microcontroller. This document provides an overview of the
MCF51AG128 series MCUs, focusing on its highly
integrated and diverse feature set.
The MCF51AG128 derivative are low-cost, low-power, and
high-performance 32-bit ColdFire V1 microcontroller units
(MCUs) designed for industrial and appliance applications. It
is an ideal upgrade for designs based on the MC9S08AC128
series of 8-bit microcontrollers.
The MCF51AG128 features the following functional units:
• 32-bit Version 1 ColdFire
®
central processor unit (CPU)
– Up to 50.33 MHz ColdFire CPU from 2.7 V to 5.5 V
– Provide 0.94 Dhrystone 2.1 DMIPS per MHz
performance when running from internal RAM (0.76
DMIPS per MHz when running from flash)
– Implements Coldfire Instruction Set Revision C
(ISA_C)
• On-chip memory
– Up to 128 KB flash memory read/program/erase over
full operating voltage and temperature
– Up to 16 KB random access memory (RAM)
– Security circuitry to prevent unauthorized access to
RAM and flash contents
• Power-Saving Modes
– Three ultra-low power stop modes and reduced power
wait mode
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
• System Protection
– Advanced independent clocked watchdog (WDOG)
with features like, robust refresh mechanism, windowed
mode, high granulation timeout, fast test of timeout, and
always forces a reset
– Additional external watchdog monitor (EWM) to help
reset external circuits
–
–
–
–
80 LQFP
14 mm
×
14 mm
64 LQFP
10 mm
×
10 mm
48 LQFP
7 mm x 7mm
64 QFP
14 mm
×
14 mm
Low-voltage detection with reset or interrupt
Separate low voltage warning with selectable trip points
Illegal opcode and illegal address detection with reset
Flash block protection for each array to prevent
accidental write/erasure
– Hardware CRC module to support fast cyclic
redundancy checks
• Debug Support
– Single-wire back ground debug interface
– Real-time debug support, with six hardware breakpoints
(4 PC, 1 address pair and 1 data) that can be configured
into a 1- or 2-level trigger
– On-chip trace buffer provides programmable start/stop
recording conditions
– Support for real-time program (and optional partial data)
trace using the debug visibility bus
• DMA Controller
– Four independently programmable DMA channels
provide the means to directly transfer data between
system memory and I/O peripherals
– DMA enabled peripherals include IIC, SCI, SPI, FTM,
HSCMP, ADC, RTC, and eGPIO, and the DMA request
from these peripherals can be configured as DMA
source or as an iEvent input
• CF1_INTC
– Support of 44 peripheral I/O interrupt requests and seven
software (one per level) interrupt requests
– Fixed association between interrupt request source, level
and priority, up to two requests can be remapped to the
highest maskable level and priority
– Unique vector number for each interrupt source
– Support for service routine interrupt acknowledge
(software IACK) read cycles for improved system
performance
– Ability to mask any individual or all interrupt sources
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
• System Clock Sources
– Oscillator (XOSC) — Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1
MHz to 16 MHz
– Internal Clock Source (ICS) — Frequency-locked-loop (FLL) controlled by internal or external reference; trimmable
internal reference allows 0.2% resolution and 2% deviation (1% across 0 to 70 ºC)
• Peripherals
– ADC — 24 analog inputs with 12 bits resolution; output formatted in 12-, 10- or 8-bit right-justified format; single or
continuous conversion (automatic return to idle after single conversion); interrupt or DMA request when conversion
complete; operation in low-power modes for lower noise operation; asynchronous clock source for lower noise operation;
selectable asynchronous hardware conversion triggers from RTC, PDB, or iEvent; dual samples based on hardware
triggers during ping-pong mode; on-chip temperature sensor
– PDB — 16-bit of resolution with prescaler; seven possible trigger events input; positive transition of trigger event signal
initiates the counter; support continuous trigger or single shot, bypass mode; supports two triggered delay outputs or ORed
together; pulsed output could be used for HSCMP windowing signal
– iEvent — User programmable combinational boolean output using the four selected iEvent input channels for use as
interrupt requests, DMA transfer requests, or hardware triggers
– FTM — Two 6-channel flexible timer/PWM modules with DMA request option; deadtime insertion is available for each
complementary channel pair; channels operate as pairs with equal outputs, pairs with complimentary outputs or
independent channels (with independent outputs); 16-bit free-running counter; the load of the FTM registers which have
write buffer can be synchronized; write protection for critical registers; backwards compatible with TPM
– TPM — 16-bit free-running or modulo up/down count operation; two channels, each channel may be input capture, output
compare, or edge-aligned PWM; one interrupt per channel plus terminal count interrupt
– CRC — High speed hardware CRC generator circuit using 16-bit shift register; CRC16-CCITT compliancy with x
16
+ x
12
+ x
5
+ 1 polynomial; error detection for all single, double, odd, and most multi-bit errors; programmable initial seed value
– HSCMP — Two analog comparators with selectable interrupt on rising edge, falling edge, or either edges of comparator
output; the positive and negative inputs of the comparator are both driven from 4-to-1 muxes; programmable voltage
reference from two internal DACs; support DMA transfer
– IIC — Compatible with IIC bus standard and SMBus version 2 features; up to 100 kbps with maximum bus loading;
multi-master operation; software programmable for one of 64 different serial clock frequencies; programmable slave
address and glitch input filter; interrupt driven byte-by-byte data transfer; arbitration lost interrupt with automatic mode
switching from master to slave; calling address identification interrupt; bus busy detection; broadcast and 10-bit address
extension; address matching causes wake-up when MCU is in Stop3 mode; DMA support
– SCI — Two serial communications interface modules with optional 13-bit break; full-duplex, standard non-return-to-zero
(NRZ) format; double-buffered transmitter and receiver with separate enables; 13-bit baud rate selection with /32
fractional divide; interrupt-driven or polled operation; hardware parity generation and checking; programmable 8-bit or
9-bit character length; receiver wakeup by idle-line or address-mark; address match feature in receiver to reduce
address-mark wakeup ISR overhead; 1/16 bit-time noise detection; DMA transmission for both transmit and receive
– SPI — Two serial peripheral interfaces with full-duplex or single-wire bidirectional option; double-buffered transmitter
and receiver; master or slave mode operation; selectable MSB-first or LSB-first shifting; 8-bit or 16-bit data modes;
programmable transmit bit rate; receive data buffer hardware match feature; DMA transmission for transmit and receive
• Input/Output
– Up to 69 GPIOs and one Input-only pin
– Interrupt or DMA request with selectable polarity on all input pins
– Programmable glitch filter, hysteresis and configurable pull up/down device on all input pins
– Configurable slew rate and drive strength on all output pins
– Independent pin value register to read logic level on digital pin
– Up to 16 rapid general purpose I/O (RGPIO) pins connected to the processor’s local 32-bit platform bus with set, clear,
and faster toggle functionality
MCF51AG128 ColdFire Microcontroller, Rev. 5
2
Freescale Semiconductor
Table of Contents
1
MCF51AG128 Family Configurations . . . . . . . . . . . . . . . . . . . .4
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .14
2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .14
2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .14
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15
2.4 Electrostatic Discharge (ESD) Protection Characteristics
16
2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .21
2.7 High Speed Comparator (HSCMP) Electricals . . . . . . .23
2.8 Digital to Analog (DAC) Characteristics . . . . . . . . . . . .23
2.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.10 External Oscillator (XOSC) Characteristics . . . . . . . . .27
2.11 ICS Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.12.2 Timer (TPM/FTM) Module Timing . . . . . . . . . . .31
2.12.3 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . .32
2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.14.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .35
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .37
5.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .37
5.2 64-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .40
5.3 64-pin QFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.4 48-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .46
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 17
Table 10. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 21
Table 11.HSCMP Electrical Specifications. . . . . . . . . . . . . . . . . 23
Table 12.5V 12-bit ADC Operating Conditions. . . . . . . . . . . . . . 23
Table 13.5 V 12-bit ADC Characteristics (V
REFH
= V
DDA
, V
REFL
=
V
SSA
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14.Oscillator Electrical Specifications (Temperature Range =
–40 to 105
°C
Ambient) . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15.ICS Frequency Specifications (Temperature Range = –40
to 105
°C
Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 17.TPM/FTM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18.SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . 32
Table 19.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 20.Orderable Part Number Summary. . . . . . . . . . . . . . . . 36
Table 21.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 22.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2
List of Figures
Figure 1. MCF51AG128 Series MCUs Block Diagram . . . . . . . . . 6
Figure 2. 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. 64-Pin QFP and LQFP . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. 48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Typical I
OH
vs. V
DD
– V
OH
(Low Drive,PTxDSn = 0) . . 19
Figure 6. Typical I
OH
vs. V
DD
– V
OH
(High Drive, PTxDSn = 1) . 19
Figure 7. Typical I
OL
vs. V
OL
(Low Drive, PTxDSn = 0) . . . . . . . 20
Figure 8. Typical I
OL
vs. V
OL
(High Drive, PTxDSn = 1) . . . . . . . 20
Figure 9. Run Current at Different Conditions. . . . . . . . . . . . . . . 22
Figure 10.ADC Input Impedance Equivalency Diagram. . . . . . . 25
Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . . 31
Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 33
Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 33
Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 34
Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 34
3
4
5
6
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 9.
MCF51AG128 Series Device Comparison. . . . . . . . . . .4
MCF51AG128 Series Functional Units . . . . . . . . . . . . . .7
Pin Availability by Package Pin-Count. . . . . . . . . . . . . .12
Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . .14
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15
ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . .16
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
MCF51AG128 ColdFire Microcontroller, Rev. 5
3
Freescale Semiconductor
MCF51AG128 Family Configurations
1
1.1
MCF51AG128 Family Configurations
Device Comparison
The following table compares the various device derivatives available within the MCF51AG128 series MCUs.
Table 1. MCF51AG128 Series Device Comparison
MCF51AG128
Feature
80-pin
Flash memory size (KB)
RAM size (KB)
ColdFire V1 core with BDM
(background debug module)
HSCMP (analog comparator)
ADC (analog-to-digital converter)
channels (12-bit)
CRC (cyclic redundancy check)
DAC
DMA controller
iEvent (intelligent Event module)
EWM (External Watchdog Monitor)
WDOG (Watchdog timer)
RTC
DBG (debug module)
IIC (inter-integrated circuit)
IRQ (interrupt request input)
INTC (interrupt controller)
LVD (low-voltage detector)
ICS (internal clock source)
OSC (crystal oscillator)
Port I/O
1
RGPIO (rapid general-purpose I/O)
SCI (serial communications interface)
SPI1 (serial peripheral interface)
SPI2 (serial peripheral interface)
FTM1 (flexible timer module) channels
FTM2 channels
Yes
No
No
6
2
6
2
69
16
53
16
39
15
2
Yes
Yes
No
No
1
1
No
Yes
Yes
Yes
Yes
Yes
69
16
53
16
39
15
2
2
1
4-ch
Yes
Yes
Yes
Yes
Yes
1
1
No
2
24
2
19
1
12
Yes
2
2
1
64-pin
128
16
Yes
2
24
2
19
1
12
48-pin
80-pin
64-pin
96
48-pin
MCF51AG96
MCF51AG128 ColdFire Microcontroller, Rev. 5
4
Freescale Semiconductor
MCF51AG128 Family Configurations
Table 1. MCF51AG128 Series Device Comparison (continued)
MCF51AG128
Feature
80-pin
TPM3 (timer pulse-width modulator)
channels
Debug Visibility Bus
1
2
MCF51AG96
48-pin
2
80-pin
64-pin
48-pin
64-pin
Yes
No
No
Yes
No
No
Up to 16 pins on Ports E and F are shared with the ColdFire Rapid GPIO module.
Some pins of FTMx might not be bonded on small package, therefore these channels could be used as soft timer only.
1.2
Block Diagram
Figure 1
shows the connections between the MCF51AG128 series pins and modules.
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
5
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