Freescale Semiconductor
Data Sheet:
Technical Data
An Energy Efficient Solution by Freescale
Document Number: MC9S08QE32
Rev. 7, 9/2011
MC9S08QE32 Series
Covers: MC9S08QE32 and
MC9S08QE16
Features
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 50.33 MHz HCS08 CPU at 3.6 V to 2.4 V, 40 MHz CPU at 2.4
V to 2.1 V and 20 MHz CPU at 2.1 V to 1.8 V across temperature
range of –40 °C to 85 °C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Flash read/program/erase over full operating voltage and
temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and flash
contents
• Power-Saving Modes
– Two very low power stop modes
– Reduced power wait mode
– Peripheral clock enable register can disable clocks to unused
modules, thereby reducing currents; allows clocks to remain enabled
to specific peripherals in stop3 mode.
– Very low power external oscillator that can be used in run, wait, and
stop modes to provide accurate clock source to real time counter.
– 6
s
typical wakeup time from stop3 mode
• Clock Source Options
– Oscillator (XOSCVLP) — Loop-control Pierce oscillator; crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16
MHz
– Internal clock source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal or
external reference; precision trimming of internal reference allows
0.2% resolution and 2% deviation over temperature and voltage;
supports CPU frequencies from
4 kHz to 50.33 MHz.
• System Protection
– Watchdog computer operating properly (COP) reset with option to
run from dedicated 1 kHz internal clock source or bus clock.
– Low-voltage warning with interrupt.
– Low-voltage detection with reset or interrupt
– Selectable trip points.
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus three breakpoints in on-chip debug
module)
MC9S08QE32
48-QFN
Case 1314
7 mm
7
mm
32-LQFP
Case 873A
7 mm
7
mm
32-QFN
Case 1582
5 mm
5
mm
44-LQFP
Case 824D
10 mm
10
mm
28-SOIC
Case 751F
– On-chip in-circuit emulator (ICE) debug module containing three
comparators and nine trigger modes. Eight deep FIFO for storing
change-of-flow addresses and event-only data. Debug module
supports both tag and force breakpoints
• Peripherals
–
ADC
— 10-channel, 12-bit resolution; 2.5s conversion time;
automatic compare function; 1.7 mV/C temperature sensor;
internal bandgap reference channel; operation in stop3; fully
functional from 3.6 V to 1.8 V
–
ACMPx
— Two analog comparators with selectable interrupt on
rising, falling, or either edge of comparator output; compare option
to fixed internal bandgap reference voltage; outputs can be
optionally routed to TPM module; operation in stop3
–
SCIx
— Two serial communications interface modules with
optional 13-bit break. Full duplex non-return to zero (NRZ); LIN
master extended break generation; LIN slave extended break
detection; wake on active edge.
–
SPI—
One serial peripheral interface; full-duplex or single-wire
bidirectional; double-buffered transmit and receive; master or
slave mode; MSB-first or LSB-first shifting
–
IIC
— One IIC; up to 100 kbps with maximum bus loading;
multi-master operation; programmable slave address; interrupt
driven byte-by-byte data transfer; supports broadcast mode and
10-bit addressing
–
TPMx
— One 6-channel (TPM3) and two 3-channel (TPM1 and
TPM2); selectable input capture, output compare, or buffered
edge- or center-aligned PWM on each channel;
–
RTC
— (Real-time counter) 8-bit modulus counter with binary or
decimal based prescaler; external clock source for precise time
base, time-of-day, calendar or task scheduling functions; free
running on-chip low power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes
• Input/Output
– 40 GPIOs, including 1 output-only pin and 1 input-only pin
– 16 KBI interrupts with selectable polarity
– Hysteresis and configurable pull up device on all input pins;
Configurable slew rate and drive strength on all output pins.
• Package Options
– 48-pin QFN, 44-pin LQFP, 32-pin LQFP/QFN, 28-pin SOIC
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008-2011. All rights reserved.
Table of Contents
1
2
3
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 9
3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . 10
3.5 ESD Protection and Latch-Up Immunity . . . . . . 12
3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Supply Current Characteristics . . . . . . . . . . . . . 16
3.8 External Oscillator (XOSCVLP) Characteristics 18
3.9 Internal Clock Source (ICS) Characteristics . . .
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . .
3.10.1Control Timing. . . . . . . . . . . . . . . . . . . . .
3.10.2TPM Module Timing . . . . . . . . . . . . . . . .
3.10.3SPI Timing. . . . . . . . . . . . . . . . . . . . . . . .
3.11 Analog Comparator (ACMP) Electricals . . . . . .
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . .
3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . .
19
20
20
21
22
26
26
29
30
30
30
4
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
1
2
Date
7/2/2008
10/7/2008
Initial public released.
Updated the Stop2 and Stop3 mode supply current, and RI
DD
in FEI mode with all modules
on at 25.165 MHz in the
Table 8
Supply Current Characteristics.
Replaced the stop mode adders section from
Table 8
with an individual
Table 9
Stop Mode
Adders with new specifications.
Updated operating voltage in
Table 7.
Added 1010 mm information to 44 LQFP in the front page.
In
Table 7,
added |I
OZTOT
|.
In
Table 11,
updated typicals and Max. for
t
IRST.
In
Table 16,
removed the Rev. Voltage High item.
Updated
Table 17.
Updated f
int_t
and f
int_ut
in the
Table 11.
Corrected the package size descriptions on the cover
Added new package of 32-pin QFN.
Description of Changes
3
4
11/4/2008
5/4/2009
5
6
7
8/27/2009
10/13/2009
9/16/2011
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08QE32RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08QE32 Series MCU Data Sheet, Rev. 7
2
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
BKGD/MS
HCS08 CORE
CPU
BDC
DEBUG MODULE (DBG)
REAL-TIME COUNTER
(RTC)
SCL
IIC MODULE (IIC)
SERIAL COMMUNICATIONS
INTERFACE MODULE(SCI1)
SERIAL COMMUNICATIONS
INTERFACE MODULE(SCI2)
SERIAL PERIPHERAL
INTERFACE MODULE(SPI)
3-CHANNEL TIMER/PWM
MODULE (TPM1)
3-CHANNEL TIMER/PWM
MODULE (TPM2)
EXTAL
XTAL
V
SSAD
V
DDAD
V
SSAD
V
DDAD
6-CHANNEL TIMER/PWM
MODULE (TPM3)
ANALOG COMPARATOR
(ACMP1)
ANALOG COMPARATOR
(ACMP2)
10-CHANNEL, 12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC12)
KEYBOARD INTERRUPT
MODULE (KBI1)
KEYBOARD INTERRUPT
MODULE (KBI2)
SDA
RxD1
TxD1
PORT B
RxD2
TxD2
SS
MISO
MOSI
SPSCK
TPM1CLK
TPM1CH2–TPM1CH0
TPM2CLK
TPM2CH2–TPM2CH0
TPM3CLK
TPM3CH5–TPM3CH0
ACMP1O
ACMP1–
ACMP1+
ACMP2O
ACMP2–
ACMP2+
ADP9–ADP0
PORT D
PORT C
PORT A
PTA7/TPM2CH2/ADP9
PTA6/TPM1CH2/ADP8
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
PTA3/KBI1P3/SCL/ADP3
PTA2/KBI1P2/SDA/ADP2
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1–
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTB3/KBI1P7/MOSI/ADP7
PTB2/KBI1P6/SPSCK/ADP6
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
PTC7/TxD2/ACMP2–
PTC6/RxD2/ACMP2+
PTC5/TPM3CH5/ACMP2O
PTC4/TPM3CH4
PTC3/TPM3CH3
PTC2/TPM3CH2
PTC1/TPM3CH1
PTC0/TPM3CH0
PTD7/KBI2P7
PTD6/KBI2P6
PTD5/KBI2P5
PTD4/KBI2P4
PTD3/KBI2P3
PTD2/KBI2P2
PTD1/KBI2P1
PTD0/KBI2P0
PTE7/TPM3CLK
PTE6
PTE5
PTE4
PTE3/SS
PTE2/MISO
PTE1/MOSI
PTE0/TPM2CLK/SPSCK
The block diagram,
Figure 1,
shows the structure of the MC9S08QE32 MCU.
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
IRQ
LVD
IRQ
USER FLASH
(MC9S08QE32 = 32768 BYTES)
(MC9S08QE16 = 16384 BYTES)
USER RAM
(MC9S08QE32 = 2048 BYTES)
(MC9S08QE16 = 1024 BYTES)
50.33 MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSCVLP)
V
SS
V
DD
VOLTAGE REGULATOR
V
SSAD
/V
REFL
V
DDAD
/V
REFH
V
REFL
V
REFH
KBI1P7–KBI1P0
KBI2P7–KBI2P0
PORT E
pins not available on 28-pin packages
pins not available on 28-pin or 32-pin packages
pins not available on 28-pin, 32-pin, or 44-pin packages
Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device.
When PTA4 is configured as BKGD, pin becomes bi-directional.
For the 28-pin packages, V
SSAD
/V
REFL
and V
DDAD
/V
REFH
are double bonded to V
SS
and V
DD
respectively.
The 48-pin package is the only package with the option of having the SPI pins (SS, MISO, MOSI, and SPSCK) available on PTE3-0 pins.
Figure 1. MC9S08QE32 Series Block Diagram
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
3
Embedded System
京公网安备 11010802033920号
EEWORLD
