EPF8636ALI84-4 datasheet, PDF - EEWORLD Datasheet

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EPF8636ALI84-4: Descriptionfpga - field programmable gate array fpga - flex 8000 63 labs 68 ios; CategoryProgrammable logic devices Programmable logic; File Size904KB，62 Pages; ManufacturerAltera (Intel)

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fpga - field programmable gate array fpga - flex 8000 63 labs 68 ios

EPF8636ALI84-4 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	LCC
package instruction	PLASTIC, LCC-84
Contacts	84
Reach Compliance Code	unknown
ECCN code	EAR99
Is Samacsys	N
Other features	636 FLIP FLOPS; 504 LOGIC ELEMENTS; CONFIGURABLE I/O OPERATION (3.3V OR 5V)
JESD-30 code	S-PQCC-J84
JESD-609 code	e0
length	29.3116 mm
Humidity sensitivity level	3
Dedicated input times	4
Number of I/O lines	64
Number of entries	68
Number of logical units	504
Output times	64
Number of terminals	84
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4 DEDICATED INPUTS, 64 I/O
Output function	REGISTERED
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC84,1.2SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	220
power supply	3.3/5,5 V
Programmable logic type	LOADABLE PLD
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	29.3116 mm
Base Number Matches	1

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FLEX 8000

Programmable Logic

Device Family

Data Sheet

January 2003, ver. 11.1

Features...

■

Low-cost, high-density, register-rich CMOS programmable logic

device (PLD) family (see

Table 1)

–

2,500 to 16,000 usable gates

–

282 to 1,500 registers

System-level features

– In-circuit reconfigurability (ICR) via external configuration

devices or intelligent controller

– Fully compliant with the peripheral component interconnect

Special Interest Group (PCI SIG)

PCI Local Bus Specification,

Revision 2.2

for 5.0-V operation

– Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)

circuitry compliant with IEEE Std. 1149.1-1990 on selected devices

– MultiVolt

I/O interface enabling device core to run at 5.0 V,

while I/O pins are compatible with 5.0-V and 3.3-V logic levels

– Low power consumption (typical specification is 0.5 mA or less in

standby mode)

Flexible interconnect

– FastTrack

Interconnect continuous routing structure for fast,

predictable interconnect delays

– Dedicated carry chain that implements arithmetic functions such

as fast adders, counters, and comparators (automatically used by

software tools and megafunctions)

– Dedicated cascade chain that implements high-speed, high-fan-in

logic functions (automatically used by software tools and

megafunctions)

– Tri-state emulation that implements internal tri-state nets

Powerful I/O pins

Programmable output slew-rate control reduces switching noise

FLEX 8000

Table 1. FLEX 8000 Device Features

Feature

Usable gates

Flipflops

Logic array blocks (LABs)

Logic elements (LEs)

Maximum user I/O pins

EPF8282A

EPF8282AV

2,500

282

208

EPF8452A

4,000

452

336

120

EPF8636A

6,000

636

504

136

EPF8820A

8,000

820

672

152

EPF81188A EPF81500A

12,000

1,188

126

1,008

184

16,000

1,500

162

1,296

208

Altera Corporation

DS-F8000-11.1

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