Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF52223
Rev. 3, 3/2011
MCF52223
MCF52223 ColdFire
Microcontroller
Supports
MCF52223 and
MCF52221
The MCF52223 microcontroller family is a member of the
ColdFire
®
family of reduced instruction set computing
(RISC) microprocessors.
This document provides an overview of the 32-bit MCF52223
microcontroller, focusing on its highly integrated and diverse
feature set.
This 32-bit device is based on the Version 2 ColdFire core
operating at a frequency up to 80 MHz, offering high
performance and low power consumption. On-chip memories
connected tightly to the processor core include up to
256 Kbytes of flash memory and 32 Kbytes of static random
access memory (SRAM). On-chip modules include:
• V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at
80 MHz running from internal flash memory with Multiply
Accumulate (MAC) Unit and hardware divider
• Universal Serial Bus On-The-Go (USBOTG)
• USB Transceiver
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
• Inter-integrated circuit (I2C™) bus interface module
• Queued serial peripheral interface (QSPI) module
• Eight-channel 12-bit fast analog-to-digital converter
(ADC)
• Four-channel direct memory access (DMA) controller
• Four 32-bit input capture/output compare timers with
DMA support (DTIM)
• Four-channel general-purpose timer (GPT) capable of
input capture/output compare, pulse width modulation
(PWM), and pulse accumulation
• Eight-channel/Four-channel, 8-bit/16-bit pulse width
modulation timer
• Two 16-bit periodic interrupt timers (PITs)
• Real-time clock (RTC) module
• Programmable software watchdog timer
• Interrupt controller capable of handling 57 sources
LQFP–64
10 mm x 10 mm
MAPBGA–81
10 mm x 10 mm
LQFP–100
14 mm x 14 mm
• Clock module with 8 MHz on-chip relaxation oscillator
and integrated phase-locked loop (PLL)
• Test access/debug port (JTAG, BDM)
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Table of Contents
1
Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .22
1.7 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .22
1.8 USB On-the-Go. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.9 I
2
C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.10 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.11 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.12 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.13 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .24
1.14 Pulse Width Modulator Signals . . . . . . . . . . . . . . . . . . .24
1.15 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . .24
1.16 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .25
1.17 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .26
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . .
2.4 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . .
2.5 EzPort Electrical Specifications . . . . . . . . . . . . . . . . . .
2.6 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . .
2.8 Clock Source Electrical Specifications . . . . . . . . . . . .
2.9 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . .
2.10 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 I
2
C Input/Output Timing Specifications . . . . . . . . . . . .
2.12 Analog-to-Digital Converter (ADC) Parameters. . . . . .
2.13 Equivalent Circuit for ADC Inputs . . . . . . . . . . . . . . . .
2.14 DMA Timers Timing Specifications . . . . . . . . . . . . . . .
2.15 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . .
2.16 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . .
2.17 Debug AC Timing Specifications . . . . . . . . . . . . . . . . .
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . .
3.1 64-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 81 MAPBGA Package . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 100-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
31
32
32
33
34
35
35
36
37
38
39
39
40
42
43
44
50
52
54
3
2
4
MCF52223 ColdFire Microcontroller, Rev. 3
2
Freescale Semiconductor
Family Configurations
1
Family Configurations
Table 1. MCF52223 Family Configurations
Module
ColdFire Version 2 Core with MAC (Multiply-Accumulate Unit)
System Clock
Performance (Dhrystone 2.1 MIPS)
Flash / Static RAM (SRAM)
Interrupt Controller (INTC)
Fast Analog-to-Digital Converter (ADC)
USB On-The-Go (USB OTG)
Four-channel Direct-Memory Access (DMA)
Software Watchdog Timer (WDT)
Programmable Interrupt Timer
Four-Channel General Purpose Timer
32-bit DMA Timers
QSPI
UART(s)
I
2
C
Eight/Four-channel 8/16-bit PWM Timer
General Purpose I/O Module (GPIO)
Chip Configuration and Reset Controller Module
Background Debug Mode (BDM)
JTAG - IEEE 1149.1 Test Access Port
1
Package
52221
52223
66, 80 MHz
up to 76
128/16 Kbytes
256/32 Kbytes
2
2
4
4
3
3
64 LQFP
81 MAPBGA
100 LQFP
81 MAPBGA
100 LQFP
1
The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is
bonded on smaller packages.
MCF52223 ColdFire Microcontroller, Rev. 3
3
Freescale Semiconductor
Family Configurations
1.1
Block Diagram
EzPD
EzPQ
EzPCK
EzPCS
GPTn
Interrupt
Controller
PADI – Pin Muxing
QSPI_DIN,
QSPI_DOUT
QSPI_CLK,
QSPI_CSn
Figure 1
shows a top-level block diagram of the device. Package options for this family are described later in this document.
EzPort
Arbiter
UTXDn
URXDn
URTSn
UCTSn
DTINn/DTOUTn
4 CH DMA
UART
0
UART
1
UART
2
I
2
C
QSPI
To/From PADI
SWT
DTIM
0
DTIM
1
DTIM
2
DTIM
3
JTAG_EN
MUX
PWMn
V2 ColdFire CPU
JTAG
TAP
IFP
OEP
MAC
PMM
AN[7:0]
ADC
32 Kbytes
SRAM
(4K16)4
V
STBY
256 Kbytes
Flash
(32K16)4
PORTS
(GPIO)
CIM
RSTI
RSTO
V
RH
V
RL
USB OTG
Edge
Port
EXTAL
PLL OCO
CLKGEN
XTAL
CLKOUT
PIT0
PIT1
GPT
PWM
CLKMOD0 CLKMOD1
To/From Interrupt Controller
Figure 1. Block Diagram
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
4
Family Configurations
1.2
1.2.1
•
Features
Feature Overview
Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions
for improved bit processing (ISA_A+)
— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 1616
32 or 3232
32 operations
— Illegal instruction decode that allows for 68-Kbyte emulation support
System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or
2-level trigger
On-chip memories
— 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply
support
— 256 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
— Software controlled disable of external clock output for low-power consumption
Universal Serial Bus On-The-Go (USB OTG) dual-mode host and device controller
— Full-speed / low-speed host controller
— USB 1.1 and 2.0 compliant full-speed / low speed device controller
— 16 bidirectional end points
— DMA or FIFO data stream interfaces
— Low power consumption
— OTG protocol logic
Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity
— Up to two stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
I
2
C module
The MCF52223 family includes the following features:
•
•
•
•
•
•
MCF52223 ColdFire Microcontroller, Rev. 3
5
Freescale Semiconductor
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