Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF5235EC
Rev. 4, 08/2009
MCF523x Integrated
Microprocessor
Hardware Specification
by: Microcontroller Solutions Group
The MCF523x is a family of highly-integrated 32-bit
microcontrollers based on the V2 ColdFire
microarchitecture. Featuring a 16 or 32 channel eTPU,
64 Kbytes of internal SRAM, a 2-bank SDRAM
controller, four 32-bit timers with dedicated DMA, a 4
channel DMA controller, up to 2 CAN modules, 3
UARTs and a queued SPI, the MCF523x family has been
designed for general purpose industrial control
applications. It is also a high-performance upgrade for
users of the MC68332. This document provides an
overview of the MCF523x microcontroller family, as
well as detailed descriptions of the mechanical and
electrical characteristics of the devices.
The MCF523x family is based on the Version 2 ColdFire
reduced instruction set computing (RISC)
microarchitecture operating at a core frequency of up to
150 MHz and bus frequency up to 75 MHz.
Contents
1
2
3
4
5
6
7
8
9
MCF523x Family Configurations . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . 9
Mechanicals/Pinouts and Part Numbers . . . . . . . . . . . . 14
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Document Revision History . . . . . . . . . . . . . . . . . . . . . . 45
© Freescale Semiconductor, Inc., 2009. All rights reserved.
MCF523x Family Configurations
1
MCF523x Family Configurations
Table 1. MCF523x Family Configurations
Module
ColdFire V2 Core with EMAC
(Enhanced Multiply-Accumulate
Unit)
Enhanced Time Processor Unit
with memory (eTPU)
System Clock
Performance (Dhrystone/2.1 MIPS)
Instruction/Data Cache
Static RAM (SRAM)
Interrupt Controllers (INTC)
Edge Port Module (EPORT)
External Interface Module (EIM)
4-channel Direct-Memory Access
(DMA)
SDRAM Controller
Fast Ethernet Controller (FEC)
Cryptography - Security module for
data packets processing
Watchdog Timer (WDT)
Four Periodic Interrupt Timers (PIT)
32-bit DMA Timers
QSPI
UART(s)
I
2
C
FlexCAN 2.0B - Controller-Area
Network communication module
General Purpose I/O Module
(GPIO)
JTAG - IEEE 1149.1 Test Access
Port
Package
2
x
x
x
x
—
—
x
x
4
x
3
x
1
x
x
160 QFP
196
MAPBGA
2
x
x
x
x
—
—
x
x
4
x
3
x
2
x
x
256
MAPBGA
MCF5232
x
MCF5233
x
MCF5234
x
MCF5235
x
16-ch
6K
32-ch
6K
16-ch
6K
32-ch
6K
up to 150 MHz
up to 144
8 Kbytes
64 Kbytes
2
x
x
x
x
x
—
x
x
4
x
3
x
1
x
x
256
MAPBGA
2
x
x
x
x
x
x
x
x
4
x
3
x
2
x
x
256
MAPBGA
2
Block Diagram
The superset device in the MCF523x family comes in a 256 mold array process ball grid array (MAPBGA)
package.
Figure
shows a top-level block diagram of the MCF5235, the superset device.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
2
Freescale Semiconductor
Features
EIM
(To/From SRAM backdoor)
CHIP
SELECTS
SDRAMC
QSPI
I2C_SDA
I2C_SCL
EBI
Arbiter
INTC0
INTC1
UnTXD
UnRXD
UnRTS
UnCTS
(To/From PADI)
FAST
ETHERNET
CONTROLLER
(FEC)
PADI – Pin Muxing
DTnOUT
DTnIN
FEC
CANRX
CANTX
eTPU
UART
0
UART
1
UART
2
I C
2
QSPI
SDRAMC
(To/From PADI)
(To/From
PADI)
4 CH DMA
DTIM
0
DTIM
1
DTIM
2
DTIM
3
D[31:0]
A[23:0]
DREQ[2:0] DACK[2:0]
MUX
R/W
BDM
JTAG_EN
V2 ColdFire CPU
DIV
EMAC
CS[3:0]
TA
TSIZ[1:0]
TEA
BS[3:0]
JTAG
TAP
(To/From PADI)
NEXUS
eTPU
64 Kbytes
SRAM
(8Kx16)x4
8 Kbytes
CACHE
(1Kx32)x2
PORTS
(GPIO)
CIM
Watchdog
Timer
(To/From Arbiter backdoor)
SKHA
FlexCAN
(x2)
RNGA
PLL
CLKGEN
(To/From INTC)
PIT0
PIT1
PIT2
PIT3
MDHA
Cryptography
Modules
MCF5235 Block Diagram
Edge
Port
3
Features
For a detailed feature list see the MCF5235 Reference Manual (MCF5235RM).
MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
Freescale Semiconductor
3
Signal Descriptions
4
Signal Descriptions
This section describes signals that connect off chip, including a table of signal properties. For a more
detailed discussion of the MCF523x signals, consult the
MCF5235 Reference Manual
(MCF5235RM).
4.1
Signal Properties
Table 2
lists all of the signals grouped by function. The “Dir” column is the direction for the primary
function of the pin. Refer to
Section 6, “Mechanicals/Pinouts and Part Numbers,”
for package diagrams.
NOTE
In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A24), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.
Table 2. MCF523x Signal Information and Muxing
Signal Name
GPIO
Alternate 1 Alternate 2 Dir.
1
MCF5232
160
QFP
MCF5232
196
MAPBGA
MCF5233
256
MAPBGA
MCF5234
256
MAPBGA
MCF5235
256
MAPBGA
Reset
RESET
RSTOUT
—
—
—
—
—
—
I
O
Clock
EXTAL
XTAL
CLKOUT
—
—
—
—
—
—
—
—
—
I
O
O
86
85
89
M14
N14
K14
P16
R16
M16
P16
R16
M16
P16
R16
M16
83
82
N13
P13
T15
T14
T15
T14
T15
T14
Mode Selection
CLKMOD[1:0]
RCON
—
—
—
—
—
—
I
I
19,20
79
G5, H5
K10
J3, J2
P13
J3, J2
P13
J3, J2
P13
External Memory Interface and Ports
A[23:21]
PADDR[7:5]
CS[6:4]
—
O
126, 125,
124
B11, C11,
D11
B14, C14,
A15
B14, C14,
A15
B14, C14,
A15
MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
4
Freescale Semiconductor
Signal Descriptions
Table 2. MCF523x Signal Information and Muxing (continued)
Signal Name
A[20:0]
GPIO
—
Alternate 1 Alternate 2
—
—
Dir.
1
O
MCF5232
160
QFP
123:115,
112:106,
102:98
MCF5232
196
MAPBGA
A12, B12,
C12, A13,
B13, B14,
C13, C14,
D12, D13,
D14, E11,
E12, E13,
E14, F12,
F13, F14,
G11, G12,
G13
MCF5233
256
MAPBGA
MCF5234
256
MAPBGA
MCF5235
256
MAPBGA
B15, B16, B15, B16, B15, B16,
C15, C16, C15, C16, C15, C16,
D16, D15, D16, D15, D16, D15,
D14, E16, D14, E16, D14, E16,
E15, E14, E15, E14, E15, E14,
E13, F15, E13, F15, E13, F15,
F14, F13, F14, F13, F14, F13,
G15, G14, G15, G14, G15, G14,
G13, H16, G13, H16, G13, H16,
H15, H14, H15, H14, H15, H14,
H13
H13
H13
K4, K3, K2,
K1, L4, L3,
L2, L1, M3,
M2, M1,
N2, N1, P2,
P1, R1
K4, K3, K2,
K1, L4, L3,
L2, L1, M3,
M2, M1,
N2, N1, P2,
P1, R1
K4, K3, K2,
K1, L4, L3,
L2, L1, M3,
M2, M1,
N2, N1, P2,
P1, R1
D[31:16]
—
—
—
O
21:24, 26:30, G1, G2, H1,
33:39
H2, H3, H4,
J1, J2, J3,
J4, K1, K2,
K3, K4, L1,
L2
42:49,
D[15:8]
PDATAH[7:0]
—
—
O
M1, N1, M2, R2, T2, N3, R2, T2, N3, R2, T2, N3,
N2, P2, L3, P3, R3, T3, P3, R3, T3, P3, R3, T3,
M3, N3,
N4, P4,
N4, P4,
N4, P4,
D[7:0]
PDATAL[7:0]
—
—
O
50:52, 56:60 P3, M4, N4, R4, T4, P5, R4, T4, P5, R4, T4, P5,
P4, L5, M5, R5, N6, P6, R5, N6, P6, R5, N6, P6,
N5, P5
R6, N7
R6, N7
R6, N7
143:140
63
97
—
96
—
—
—
—
B6, C6, D7, C9, B9, A9, C9, B9, A9, C9, B9, A9,
C7
A10
A10
A10
N6
H11
J14
J13
P6
P7
H13
H12
T7
K14
K13
L16
N8
P8
K16
K15
T7
K14
K13
L16
N8
P8
K16
K15
T7
K14
K13
L16
N8
P8
K16
K15
BS[3:0]
OE
TA
TEA
R/W
TSIZ1
TSIZ0
TS
TIP
PBS[7:4]
PBUSCTL7
PBUSCTL6
PBUSCTL5
PBUSCTL4
PBUSCTL3
PBUSCTL2
PBUSCTL1
PBUSCTL0
CAS[3:0]
—
—
DREQ1
—
DACK1
DACK0
DACK2
DREQ0
—
—
—
—
—
—
—
—
—
O
O
I
I
O
O
O
O
O
Chip Selects
CS[7:4]
CS[3:2]
CS1
CS0
PCS[7:4]
PCS[3:2]
PCS1
—
—
SD_CS[1:0]
—
—
—
—
—
—
O
O
O
O
—
134,133
130
129
B9, A10,
C10, A11
A9, C9
B10
D10
C12, A13,
C13, A14
B12, D12
B13
D13
C12, A13,
C13, A14
B12, D12
B13
D13
C12, A13,
C13, A14
B12, D12
B13
D13
SDRAM Controller
MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
Freescale Semiconductor
5
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