TECHNICAL NOTE
Video / Audio Interfaces for TV and DVD Recorders
NTSC-PAL Audio I/O
Interface for Recording
BD3823FV
Description
BD3823FV is a low-noise (3.2μVrms), low distortion (0.0015%), 5ch selector, incorporating a resistor-ladder type
volume.
Because of a wide power supply voltage range (7V to 14.5V), BD3823FV can meet a wide input voltage (to 4.5 Vms), and high S/N
can be achieved. In addition, the built-in volume does not add any distortion ratio characteristics, even when the attenution is varied,
and is applicable for high-quality audio systems.
Features
1) A resistor-ladder type volume circuit is with a low distortion ratio (0.0015% with volume set to –6dB) and low noise (3.2 Vrms with
volume set to -6dB).
2) By grouping sound input terminals with output terminals, the PCB layout is reduced.
3) Small package SSOP - B20 achieves good crosstalk characteristicss (-110 dB).
4) The use of Bi-CMOS process enables low current consumption and energy saving design.
Because of low current consumption, BD3823FV has the advantage in quality over the scaling down of the internal regulators and
heat controls.
Applications
DVD recorders
Absolute maximum rating
(T
a
=25°C)
Parameter
Symbol
Limits
Unit
VCC
15.0
Applied Voltage
V
SCL, SDA
7.0
Input voltage
V
IN
V
VCC+0.3 GND-0.3
*
1
Power Dissipation
P
d
810
mW
*
2
Operating Temperature
T
opr
°C
-40 +85
Storage Temperature
T
astg
°C
-55 +150
*1 Reduced by 6.5 mW/ C at 25 C or higher.
Thermal resistance ja = 154 (°C/W), when Rohm standard board is mounted.
Rohm standard board: Size: 70 70 1.6 (mm
3
)
Material: FR4 glass-epoxy substrate (copper foil area: not more than 3%).
*2 As long as voltage stays within operating voltage range, certain circuit operation is guaranteed in
the operating temperature range.
Allowable power loss conditions are related to temperature, to which care must be taken.
In addition though the standard value of its electrical characteristics cannot be guaranteed under
the conditions other than those specified, basic functions are maintained.
Operating range
(Basic operation at Ta=25 )
Parameter
Symbol
Min.
Typ.
Max.
Unit
*
3
Power supply voltage
VCC
7.0
12.0
14.5
V
*3 As long as temperature and operating voltage meet specifications
In addition, though the standard value of its electrical characteristics cannot be guaranteed under
the conditions other than those specified, basic functions are maintained.
Ver.B Oct.2005
Electrical characteristics
Unless otherwise specified, Ta=25 , VCC=12V, f=1kHz, Vin=1Vrms, Rg=600 , R
L
=10k , Gain selector = 0dB, Volume = 0dB,
Input terminal = Front 1, Output terminal = Out 1
Limits
Parameter
Symbol
Min.
Circuit Current upon no signal
Voltage gain
Maximum output voltage
Channel balance
Total harmonic distortion
GENERAL
Output noise voltage *
Residual output noise voltage *
Cross-talk between channels *
Input impedance
I
Q
G
V
V
OM
CB
THD
V
NO
V
NOR
CTC
R
IN
-
-1.5
3.0
-1.5
-
-
-
-
77
Typ.
2.5
0
3.6
0
0.0015
Unit
Max.
10
1.5
-
1.5
0.05
16
10
-80
143
mA
B
Vrms
dB
%
Vrms
Vrms
dB
k
Conditions
V
IN
=0Vrms
G
V
=20log(V
OUT
/V
IN
)
V
OM
at THD(V
OUT
)=1%
BW=400Hz-30KHz
CB = G
V1
-G
V2
G
V1
:ch1Gain, G
V2
:ch2 Gain
V
IN
=2Vrms,Volume=-6dB
BW=400Hz-30KHz
Volume=-6dB
R
g
= 0 , BW=IHF-A
Volume = - dB
R
g
= 0 , BW=IHF-A
R
g
= 0
BW = IHF-A
1pin-10pin terminal
V
IM
at THD(V
OUT
)=1%
BW=400Hz-30KHz
1pin-10pin terminal
R
g
= 0
BW = IHF-A
CTS=20log(V
OUT
/V
IN
)
GV=20log(V
OUT
/V
IN
)
BW = IHF-A
Volume = - dB
GV=20log(V
OUT
/V
IN
)
BW = IHF-A
Volume=0 -30.5dB
Volume=0 -30.5dB
Gain Selector=6dB
V
IN
=500mVrms
G=20log(V
OUT
/V
IN
)
From 2dB to 4dB
3.2
2
-110
110
1)
Maximum input voltage
V
IM
3.1
3.6
-
Vrms
Cross-talk between selectors *
CTS
-
-110
-80
dB
Volume control range
V
V
-32.5
-30.5
-28.5
dB
VOLUME
Maximum attenuation *
G
V MIN
-
-106
-85
dB
Step resolution
Attenuation set error
G
V STEP
G
V ERR
-
-1.5
0.5
0
-
1.5
dB
dB
GAIN SELECTOR
Maximum gain
G
MAX
4.5
6
7.5
dB
Step resolution
Gain set error
G
STEP
G
ERR
-
-1.5
2
0
-
1.5
dB
dB
VP-9690A (average value detection, effective value display) filter by Matsushita Communication is used for * measurement.
Phase between input/output is the same.
This IC is not designed to be radiation-resistant.
1)V
IM
=2.5Vrms(TYP) at VCC=9V THD(V
OUT
)=1%
V
IN
=4.2Vrms(TYP) at VCC=14V THD(V
OUT
)=1%
2/8
Timing chart
Electrical specifications and timing of bus lines and I/O stages
Fig.1 Timing Definition on I
2
C BUS
2
Table 1 . Characteristics of the SDA and SCL BUS lines for I C BUS devices
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition. After this period, the first clock
pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
Symbol
f
SCL
t
BUF
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU; DAT
t
R
t
F
t
SU;STO
C
b
High speed mode
I
2
C BUS
Min.
0
1.3
0.6
1.3
0.6
0.6
0*
100
20+Cb
20+Cb
0.6
-
Max.
400
-
-
-
-
-
-
-
300
300
-
400
Unit
kHz
s
s
s
s
s
s
ns
ns
ns
s
pF
The above numerical values all correspond to V
IH min
and V
IL max
levels (see Table 2).
*The input signals must internally provide at least 300 ns hold-time for SDA signals (at V
IH min
of SCL signals) in order to cross over
undefined region at the fall-end of SCL.
Table 2. Characteristics of the SDA and SCL I/O stages for I C BUS devices
High speed mode
Parameter
Symbol
I2C BUS
Min.
Max.
-0.5
2.3
n/a
0
0
20+0.1Cb
-10
-
1.0
-
n/a
50
0.4
250
10
10
Unit
2
13
14
15
16
17
18
19
20
Low-level input voltage : fixed input levels
Low-level input voltage : fixed input levels
Hysteresis of Schmitt trigger inputs: fixed input levels
Pulse width of spikes which must be suppressed by the input filter.
Low-level output voltage (open drain): at 3mA sink current
Output fall time from VIHmin. to VIHmax. with a bus capacitance from 10
pF to 400pF: with up to 3mA sink current at VOL1
Input current each I/O pin with an input voltage between 0.4V and 0.9
VCCmax.
Capacitance for each I/O pin
V
IL
V
IH
V
s
V
ns
V
ns
A
pF
V
hys
t
SP
V
OL1
t
OF
I
i
C
i
n/a = not applicable
3/8
2
I C BUS FORMAT
MSB
S
1bit
S
8bit
LSB
Slave Address
1bit
MSB
A
8bit
LSB
Select Address
MSB
A
1bit
LSB
Data
8bit
A
P
1bit 1bit
= Start condition (Recognition of start bit)
Least significant bit is “L” for writing.
Slave Address = Recognition of slave address. 7 bits in upper order are voluntary.
A
Select Address
Data
P
= ACKNOWLEDGE bit (Recognition of acknowledgement)
Selection of volume, etc.
Data such as volume, etc.
= Stop condition (Recognition of stop bit)
I
2
C BUS Interface Protocol
1 Basic form
S
Slave Address
MSB
LSB
A
Select Address
MSB
LSB
A
Data
A
MSB
LSB
P
2
Automatic increment (Select Address increases (+1) according to the number of data.
S
Slave Address A Select Address A
MSB
LSB
MSB
LSB MSB
Data1
LSB
A
MSB
Data2
LSB
A
MSB LSB
DataN
A
P
[1] Data 1 shall be set as data of address specified by Select Address.
[2] Data 2 shall be set as data of address specified by Select Address +1.
[3] Data N shall be set as data of address specified by Select Address +N-1.
Slave Address
Because the slave address can be changed by the SELECT setting, it is possible to use two chips simultaneously on a single
control BUS .
MSB
LSB
SELECTvoltage condition
A6
A5
A4
A3
A2
A1
A0
R/W
GND
0.2×VCC
1
0
0
0
0
0
0
0
0.8×VCC
VCC
1
0
0
0
0
1
0
0
Set the SELECT voltage within the condition defined.
Data format
Select
Address
(HEX)
00
01
02
03
MSB
D7
D6
D5
Data
D4
D3
D2
D1
Input Selector
LSB
D0
Items to be set
Input Selector
Volume ch1
Volume ch2
Gain Selector
*Don’t care
*
*
*
*
*
*
*
*
*
*
*
Volume attenuation ch1
Volume attenuation ch2
*
*
*
*
Gain Selector
4/8
Application circuit diagram
V
CC
DVD
A/D
SELECT
OUT1
OUT2
V
CC
VRR
FILTER
AGND
SCL
SDA
DGND
80HEX 84HEX
10
10
10
10
10
V
CC
Regulator
AGND
I
2
C
LOGIC
DGND
1/2V
CC
0
-30.5dB/0.5dB step -
0
-30.5dB/0.5dB step -
GAIN SELECTOR
0, 2, 4, 6dB
INPUT
1
1
1
1
1
1
1
1
1
1
Front1
Front2
Tuner1
Tuner2
EXT11
EXT12
EXT21
EXT22
EXT31
EXT32
Fig.2 Application Circuit Diagram
Pin No. Pin Name
1
2
3
4
5
6
7
8
9
10
Front1
Front2
Pin Description
Front 1ch input terminal
Front 2ch input terminal
Pin No.
11
12
13
14
15
16
17
18
19
20
Pin Name
DGND
SDA
SCL
AGND
Pin Description
Ground ternial
I
2
C communication data terminal
I C communication clock
terminal
Ground terminal
2
Tuner1 Tuner 1 ch input
Tuner2 Tuner 2 ch input
EXT11 External 1 1ch input terminal
EXT12 External 1 2ch input terminal
EXT21 External 2 1ch input terminal
EXT22 External 2 2ch input terminal
EXT31 External 3 1ch input terminal
EXT32 External 3 2ch input terminal
FILTER 1/2V
CC
terminal
VRR
V
CC
OUT2
OUT1
Ripple filter terminal
Power supply terminal
Volume 2ch output terminal
Volume 1ch output terminal
SELECT Slave address selection terminal
5/8
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