PEX 8311-AA66BC F datasheet, PDF

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PEX 8311-AA66BC F: Descriptionpci interface IC pex 8311 chip; Categorysemiconductor Other integrated circuit (IC); File Size2MB，5 Pages; ManufacturerPLX Technology, Inc. (Broadcom ); Environmental Compliance

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PEX 8311-AA66BC F Overview

pci interface IC pex 8311 chip

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Version 1.2 2005

PEX 8311

PCI Express to Generic Local Bus Bridge

Multi-purpose and Feature-Rich PCI Express Bridge

The bridge offers PCI Express™ (PCIe) bridging capability from a Generic

Local Bus to PCIe enabling users to add scalable high bandwidth

interconnection to a wide variety of applications including communication

line cards, surveillance systems, video capture cards, industrial control, office

automation, IP Media Servers, RAID systems and medical imaging. Many

embedded system designs utilizing PCI today can easily migrate to PCIe. The

ExpressLane™ PEX 8311 bridge can be used in Root Complex mode with the

device directly interfacing multiple local bus devices including processors and

FPGAs to a downstream PCIe port. The bridge can also function in an EndPoint

type application connecting multiple local bus components to an upstream PCIe

port.

Highly Flexible, Generic Local Bus

The PEX 8311 offers a highly flexible yet low overhead generic Local Bus

which provides a direct connection to two generic industry-standard

interconnect buses. The bus protocol can be set to the non-multiplexed

address and data mode with up to 32-bit transfers “C-Mode” or multiplexed

address/data with up to 32-bit transfers “J-Mode”. This bus can be directly

connected to many processors with minimal or no glue logic. Memory,

FPGAs, FIFOs and other devices can be simultaneously placed on this bus.

Dual Independent DMA Channels

The PEX 8311 provides two data transfer channels each with internal

independent programmable FIFOs. These channels provide independent data

transfers with the bridge initiating both the PCIe and local bus. With dual

channels, data from two different sources or bidirectional traffic can be

transferred simultaneously without the need to finish one transfer before

starting the second. Each DMA channel can use independent scatter-gather

descriptor lists for increased flexibility. The use of DMA descriptors allows

the two channels to look like multiple virtual DMA channels.

Complete Conversion from PCI Express Signaling

The PEX 8311 provides a complete local bus to PCIe translation. The bridge

is equipped with a standard PCIe port that operates as a single x1 link with a

maximum of 250 Megabytes per second of throughput per transmit and

receive directions. The single 2.5 Gbps integrated SerDes delivers the highest

bandwidth with the lowest possible pin-count. The device supports internal

queues with flow control features to optimize throughput and traffic flow.

Root Complex and EndPoint Modes

The PEX 8311 bridge supports both Root Complex and EndPoint modes of

operation. This flexibility allows a Root Complex system designer to utilize

the part as a type of “north bridge” whereby multiple Local Bus components

present including a processor, FPGAs, memory, DSP, etc., can communicate with

each other as well with downstream PCIe devices. In this case, the bridge’s

configuration and system hierarchy comes through the Local Bus. In EndPoint

mode, the bridge is configured through the PCIe port.

Features

PEX 8311 Key Features

PCI Express to Generic Local Bus Bridge

Root Complex and EndPoint Modes of

Operation

Local Bus modes:

32-bit address & 32-bit data C Mode

Multiplexed 32-bit address/data J Mode

Local Bus Clock rates to 66MHz

Zero wait state bursts to 264 MB/sec

1 Lane PCI Express Port

2 DMA Channels

Integrated SerDes

21mmx21mm, 337 pin PBGA package

3.3V I/O and 5V tolerant Local Bus

Power: 1.0 Watt

PEX 8311 Additional Features

Integrated PCI Express Interface

Compliant to PCIe Specification, r1.0a

x1 Link, dual-simplex, 2.5 Gbps/direction

Auto Polarity reversal

128 Byte payload maximum

Link CRC support

Link/Device power management

Flow control buffering

PCIe transaction queues for eight

outstanding TLPs

VGA/ISA Enable Registers

On-the-fly Endian conversion

Multiple DMA operational modes

Block and scatter/gather transfers

DMA descriptor ring management

Demand mode & EOT H/W controls

Direct Master data transfers

Read ahead and programmable read pre-

fetch counter

Generate any PCIe transaction

Direct Slave data transfers

8-,16-, and 32-bit local bus access

Writes, read ahead, posted writes,

programmable read pre-fetch counter

Control

Eight mailbox and two doorbell registers

Root Complex or EndPoint mode

reset/interrupt

Serial EEPROM Interface

DC JTAG Boundary Scan

Four GPIO Pins, 1 GPO, 1 GPI

I2O Messaging Unit

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