– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Support PCI Power Management Interface specification (PCI-
PM 1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Block Diagram
5-Port Switch Core / 6 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
Phy
Logical
Layer
Mux / Demux
Phy
Logical
Layer
Mux / Demux
Phy
Logical
Layer
Mux / Demux
Phy
Logical
Layer
Mux / Demux
Phy
Logical
Layer
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
(Port 0)
(Port 2)
(Port 3)
Figure 1 Internal Block Diagram
(Port 4)
(Port 5)
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 28
2014 Integrated Device Technology, Inc.
June 18, 2014
IDT 89HPES6T5 Data Sheet
u
u
11 General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 15mm x 15mm 196-ball BGA with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES6T5 provides the most efficient I/O connectivity solution for applications requiring high
throughput, low latency, and simple board layout with a minimum number of board layers. It provides 3 GBps (24 Gbps) of aggregated, full-duplex
switching capacity through 6 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both direc-
tions and is fully compliant with PCI Express Base specification revision 1.1.
The PES6T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac-
tion layers in compliance with PCI Express Base specification Revision 1.1. The PES6T5 can operate either as a store and forward or cut-through
switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management to allow efficient switching for applications requiring additional narrow port connectivity.
Processor
Processor
North
Bridge
Memory
Memory
Memory
Memory
South
Bridge
x2
PES6T5
x1
GE
LOM
x1
GE
LOM
x1
GE
x1
1394
Figure 2 I/O Expansion Application
SMBus Interface
The PES6T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES6T5, allowing every
configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of
the PES6T5 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an
external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Table 1.
2 of 28
June 18, 2014
IDT 89HPES6T5 Data Sheet
Bit
1
2
3
4
5
6
7
Slave
SMBus
Address
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
0
SSMBADDR[5]
1
1
Master
SMBus
Address
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
1
0
1
Table 1 Master and Slave SMBus Address Assignment
As shown in
Figure 3,
the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in
Figure
3(a),
the master and slave SMBuses are tied together and the PES6T5 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES6T5 registers supports SMBus arbitration. In some systems, this SMBus master
interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support
these systems, the PES6T5 may be configured to operate in a split configuration as shown in
Figure 3(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES6T5 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the
serial EEPROM.
PES6T5
Processor
SMBus
Master
Serial
EEPROM
...
Other
SMBus
Devices
PES6T5
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES6T5 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES6T5 utilizes
an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when-
ever the state of a Hot-Plug output needs to be modified, the PES6T5 generates an SMBus transaction to the I/O expander with the new value of all of
the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate
function of GPIO) of the PES6T5. In response to an I/O expander interrupt, the PES6T5 generates an SMBus transaction to read the state of all of the
Hot-Plug inputs from the I/O expander.
3 of 28
June 18, 2014
IDT 89HPES6T5 Data Sheet
General Purpose Input/Output
The PES6T5 provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may
be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate
functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES6T5. Some of the functions listed may be multiplexed onto the same pin. The
active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.
All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
PE0RP[1:0]
PE0RN[1:0]
PE0TP[1:0]
PE0TN[1:0]
PE2RP[0]
PE2RN[0]
PE2TP[0]
PE2TN[0]
PE3RP[0]
PE3RN[0]
PE3TP[0]
PE3TN[0]
PE4RP[0]
PE4RN[0]
PE4TP[0]
PE4TN[0]
PE5RP[0]
PE5RN[0]
PE5TP[0]
PE5TN[0]
PEREFCLKP
PEREFCLKN
Type
I
O
I
O
I
O
I
O
I
O
I
Name/Description
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive
pairs for port 0.
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 0.
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive
pair for port 2.
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 2.
PCI Express Port 3 Serial Data Receive.
Differential PCI Express receive
pair for port 3.
PCI Express Port 3 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 3.
PCI Express Port 4 Serial Data Receive.
Differential PCI Express receive
pair for port 4.
PCI Express Port 4 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 4.
PCI Express Port 5 Serial Data Receive.
Differential PCI Express receive
pair for port 5.
PCI Express Port 5 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 5.
PCI Express Reference Clock.
Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select.
This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
REFCLKM
I
4 of 28
June 18, 2014
IDT 89HPES6T5 Data Sheet
Signal
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
Type
I
I/O
I/O
I
I/O
I/O
Name/Description
Master SMBus Address.
These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock.
This bidirectional signal is used to synchronize
transfers on the master SMBus.
Master SMBus Data.
This bidirectional signal is used for data on the mas-
ter SMBus.
Slave SMBus Address.
These pins determine the SMBus address to
which the slave SMBus interface responds.
Slave SMBus Clock.
This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Slave SMBus Data.
This bidirectional signal is used for data on the slave
SMBus.
Table 3 SMBus Interface Pins
Signal
GPIO[0]
Type
I/O
Name/Description
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
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