XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE
MAY 2007
REV. 1.0.2
GENERAL DESCRIPTION
The XR16V2651
1
(V2651) is a high performance dual
universal asynchronous receiver and transmitter
(UART) with 32 byte TX and RX FIFOs. The device
operates from 2.25 to 3.6 volts with 5 Volt tolerant
inputs and is pin-to-pin and software compatible to
Exar’s XR16V2551 and XR16L2551. The device
includes 2 additional capabilities over the
XR16V2650: Intel and Motorola data bus selection
and a “PowerSave” mode to further reduce sleep
current to a minimum during sleep mode. It supports
the Exar’s enhanced features of selectable FIFO
trigger level, automatic hardware (RTS/CTS) and
software flow control, and a complete modem
interface. An internal loopback capability allows
system diagnostics. Independent programmable
fractional baud rate generators are provided in each
channel to select data rates up to 16 Mbps at 3.3 Volt
and 4X sampling clock. The V2651 is available in 48-
pin TQFP and 32-pin QFN packages.
N
OTE
:
1 Covered by U.S. Patent #5,649,122
FEATURES
•
2.25 to 3.6 Volt Operation
•
5 Volt Tolerant Inputs
•
Pin-to-pin compatible to Exar’s XR16L2751 in the
48-TQFP package
•
Two independent UART channels
■
■
Register set identical to 16V2650
Data rate of up to
16 Mbps at 3.3 V,
and
12.5
Mbps at 2.5 V
with 4X sampling rate
Fractional Baud Rate Generator
Transmit and Receive FIFOs of 32 bytes
Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode with wake-up interrupt
Full modem interface
■
■
■
■
■
■
■
■
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. XR16V2651 B
LOCK
D
IAGRAM
•
PowerSave Feature reduces sleep current to 15 µA
•
Device Identification and Revision
•
Crystal oscillator (up to 32MHz) or external clock
(up to 64MHz) input
•
48-TQFP and 32-QFN packages
PwrSave
A2:A0
D7:D0
IOR# (VCC)
IOW# (R/W#)
CSA# (CS#)
CSB# (A3)
INTA (IRQ#)
INTB (logic 0)
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset (Reset#)
16/68#
CLKSEL
Intel or
Motorola
Data Bus
Interface
*5 Volt Tolerant Inputs
2.25 to 3.6V VCC
GND
UART Channel A
UART
Regs
BRG
32 Byte TX FIFO
TX & RX
IR
ENDEC
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
32 Byte RX FIFO
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
CTSA#
VCC
CTSA#
VCC
REV. 1.0.2
D4
D3
D2
D1
D5
D0
D4
D5
D3
D2
D1
30
29
D0
26
32
31
28
30
29
26
32
31
28
D6
D7
RXB
RXA
TXA
TXB
CSA#
CSB#
27
25
27
25
1
2
3
4
5
6
7
8
13
11
16
12
14
10
15
9
24
23
RESET
RTSA#
INTA
INTB
A0
A1
A2
16/68#
VCC
D6
D7
RXB
RXA
TXA
TXB
CS#
A3 (CSB#)
1
2
3
4
5
6
7
8
11
13
12
14
RTSB# 15
10
16
9
24
23
22
RESET# (Reset)
RTSA#
IRQ#
NC (INTB)
A0
A1
A2
16/68#
GND
XR16V2651
32-pin QFN
In 16 (Intel) Mode
22
21
20
19
18
17
XR16V2651
32-pin QFN
in 68 (Motorola) Mode
21
20
19
18
17
PWRSAVE
GND
43 TXRDYA#
43 TXRDYA#
DSRA#
VCC (IOR#)
PWRSAVE
RTSB#
CTSB#
XTAL2
XTAL1
38 CTSA#
DSRA#
CTSB#
38 CTSA#
XTAL2
40 CDA#
XTAL1
IOW#
R/W#
GND
IOR#
41 RIA#
41 RIA#
42 VCC
42 VCC
37 NC
40 CDA#
39
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CSA#
CSB#
PWRSAVE
1
2
3
4
5
6
7
8
9
10
11
12
IOW# 15
IOR# 19
XTAL1 13
RXRDYB# 18
20
RTSB# 22
CTSB# 23
CDB# 16
RIB# 21
XTAL2 14
GND 17
16/68#
24
36 RESET
35 DTRB#
34 DTRA#
33 RTSA#
39
37 NC
48 D4
47 D3
46 D2
45 D1
44 D0
48 D4
47 D3
46 D2
45 D1
44 D0
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CS#
A3
PWRSAVE
1
2
3
4
5
6
7
8
9
10
11
12
R/W# 15
XTAL1 13
RXRDYB# 18
NC 19
20
RTSB# 22
CTSB# 23
CDB# 16
XTAL2 14
RIB# 21
GND 17
16/68#
24
36 RESET#
35 DTRB#
34 DTRA#
33 RTSA#
XR16V2651
48-pin TQFP
in 16 (Intel) Mode
32 OP2A#
31 RXRDYA#
30 INTA
29 INTB
28 A0
27 A1
26 A2
25 CLKSEL
XR16V2651
48-pin TQFP
in 68 (Motorola) Mode
32 OP2A#
31 RXRDYA#
30 IRQ#
29 NC
28 A0
27 A1
26 A2
25 CLKSEL
DSRB#
VCC
DSRB#
GND
ORDERING INFORMATION
P
ART
N
UMBER
XR16V2651IL32
XR16V2651IM
P
ACKAGE
32-Pin QFN
48-Lead TQFP
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
2
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
PIN DESCRIPTIONS
Pin Description
N
AME
32-QFN 48-TQFP
T
YPE
P
IN
#
P
IN
#
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(VCC)
18
19
20
2
1
32
31
30
29
28
27
14
26
27
28
3
2
1
48
47
46
45
44
19
I
Address data lines [2:0]. These 3 address lines select one of the internal registers
in UART channel A/B during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
When 16/68# pin is HIGH, the Intel bus interface is selected and this input
becomes read strobe (active low). The falling edge instigates an internal read cycle
and retrieves the data byte from an internal register pointed by the address lines
[A2:A0], puts the data byte on the data bus to allow the host processor to read it on
the rising edge.
When 16/68# pin is LOW, the Motorola bus interface is selected and this input is
not used and should be connected to VCC.
When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write
strobe (active low). The falling edge instigates the internal write cycle and the rising
edge transfers the data byte on the data bus to an internal register pointed by the
address lines.
When 16/68# pin is LOW, the Motorola bus interface is selected and this input
becomes read (HIGH) and write (LOW) signal.
When 16/68# pin is HIGH, this input is chip select A (active low) to enable channel
A in the device.
When 16/68# pin is LOW, this input becomes the chip select (active low) for the
Motorola bus interface.
When 16/68# pin is HIGH, this input is chip select B (active low) to enable channel
B in the device.
When 16/68# pin is LOW, this input becomes address line A3 which is used for
channel selection in the Motorola bus interface. Input logic 0 selects channel A and
logic 1 selects channel B.
When 16/68# pin is HIGH for Intel bus interface, this output becomes channel A
interrupt output. The output state is defined by the user through the software set-
ting of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when
MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic
1 when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this output becomes device
interrupt output (active low, open drain). An external pull-up resistor is required for
proper operation.
IOW#
(R/W#)
12
15
I
CSA#
(CS#)
7
10
I
CSB#
(A3)
8
11
I
INTA
(IRQ#)
22
30
O
3
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
Pin Description
N
AME
INTB
32-QFN 48-TQFP
T
YPE
P
IN
#
P
IN
#
21
29
O
D
ESCRIPTION
UART channel B Interrupt output. The output state is defined by the user through
the software setting of MCR[3]. INTB is set to the active mode and OP2B# output
LOW when MCR[3] is set to a logic 1. INTB is set to the three state mode and
OP2B# output HIGH when MCR[3] is set to a logic 0 (default). See MCR[3].
UART channel A Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel A. See
Table 3
. If it is not used, leave it uncon-
nected.
UART channel A Receiver Ready (active low). This output provides the RX FIFO/
RHR status for receive channel A. See
Table 3
. If it is not used, leave it uncon-
nected.
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B. See
Table 4
. If it is not used, leave it uncon-
nected.
UART channel B Receiver Ready (active low). This output provides the RX FIFO/
RHR status for receive channel B. See
Table 3
. If it is not used, leave it uncon-
nected.
REV. 1.0.2
TXRDYA#
-
43
O
RXRDYA#
-
31
O
TXRDYB#
-
6
O
RXRDYB#
-
18
O
MODEM OR SERIAL I/O INTERFACE
TXA
5
7
O
UART channel A Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.
UART channel A Receive Data or infrared receive data. Normal receive data input
must idle HIGH. The infrared receiver pulses typically idles at LOW but can be
inverted by software control prior going into the decoder, see MCR[6]. If this pin is
not used, tie it to VCC or pull it high via a 100k ohm resistor.
UART channel A Request-to-Send (active low) or general purpose output. This out-
put must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
and IER[6].
UART channel A Clear-to-Send (active low) or general purpose input. It can be
used for auto CTS flow control, see EFR[7], and IER[7]. This input should be con-
nected to VCC when not used.
UART channel A Data-Terminal-Ready (active low) or general purpose output. If it
is not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel A Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel A Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
RXA
4
5
I
RTSA#
23
33
O
CTSA#
25
38
I
DTRA#
DSRA#
CDA#
RIA#
-
-
-
-
34
39
40
41
O
I
I
I
4
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
Pin Description
N
AME
OP2A#
32-QFN 48-TQFP
T
YPE
P
IN
#
P
IN
#
-
32
O
D
ESCRIPTION
Output Port 2 Channel A - The output state is defined by the user and through the
software setting of MCR[3]. INTA is set to the active mode and OP2A# output LOW
when MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A#
output HIGH when MCR[3] is set to a logic 0. See MCR[3]. If INTA is used, this out-
put should not be used as a general output else it will disturb the INTA output func-
tionality.
UART channel B Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.
UART channel B Receive Data or infrared receive data. Normal receive data input
must idle HIGH. The infrared receiver pulses typically idles at logic 0 but can be
inverted by software control prior going in to the decoder, see MCR[6]. If this pin is
not used, tie it to VCC or pull it high via a 100k ohm resistor.
UART channel B Request-to-Send (active low) or general purpose output. This port
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1], and
IER[6].
UART channel B Clear-to-Send (active low) or general purpose input. It can be
used for auto CTS flow control, see EFR[7], and IER[7]. This input should be con-
nected to VCC when not used.
UART channel B Data-Terminal-Ready (active low) or general purpose output. If it
is not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
Output Port 2 Channel B - The output state is defined by the user and through the
software setting of MCR[3]. INTB is set to the active mode and OP2B# output LOW
when MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B#
output HIGH when MCR[3] is set to a logic 0. See MCR[3]. If INTB is used, this out-
put should not be used as a general output else it will disturb the INTB output func-
tionality.
TXB
6
8
O
RXB
3
4
I
RTSB#
15
22
O
CTSB#
16
23
I
DTRB#
DSRB#
CDB#
RIB#
OP2B#
-
-
-
-
-
35
20
16
21
9
O
I
I
I
O
ANCILLARY SIGNALS
XTAL1
XTAL2
PwrSave
10
11
9
13
14
12
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
PowerSave (active high). This feature isolates the V2651’s data bus interface from
the host preventing other bus activities that cause higher power drain during sleep
mode. See Sleep Mode with Auto Wake-up and PowerSave Feature section for
details.
5
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