Precision
Instrumentation Amplifier
AD524
FEATURES
Low noise: 0.3 μV p-p at 0.1 Hz to 10 Hz
Low nonlinearity: 0.003% (G = 1)
High CMRR: 120 dB (G = 1000)
Low offset voltage: 50 μV
Low offset voltage drift: 0.5 μV/°C
Gain bandwidth product: 25 MHz
Pin programmable gains of 1, 10, 100, 1000
Input protection, power-on/power-off
No external components required
Internally compensated
MIL-STD-883B and chips available
16-lead ceramic DIP and SOIC packages and 20-terminal
leadless chip carrier available
Available in tape and reel in accordance with EIA-481A
standard
Standard military drawing also available
– INPUT
1
G = 10
13
G = 100
12
G = 1000
11
RG
1 16
RG
2 3
FUNCTIONAL BLOCK DIAGRAM
PROTECTION
4.44kΩ
404Ω
40Ω
V
b
20kΩ
20kΩ
OUTPUT
20kΩ
20kΩ
20kΩ
20kΩ
SENSE
AD524
REFERENCE
00500-001
+ INPUT
2
PROTECTION
Figure 1.
GENERAL DESCRIPTION
The AD524 is a precision monolithic instrumentation amplifier
designed for data acquisition applications requiring high accu-
racy under worst-case operating conditions. An outstanding
combination of high linearity, high common-mode rejection,
low offset voltage drift, and low noise makes the AD524 suitable
for use in many data acquisition systems.
The AD524 has an output offset voltage drift of less than
25 μV/°C, input offset voltage drift of less than 0.5 μV/°C, CMR
above 90 dB at unity gain (120 dB at G = 1000), and maximum
nonlinearity of 0.003% at G = 1. In addition to the outstanding
dc specifications, the AD524 also has a 25 kHz bandwidth
(G = 1000). To make it suitable for high speed data acquisition
systems, the AD524 has an output slew rate of 5 V/μs and settles
in 15 μs to 0.01% for gains of 1 to 100.
As a complete amplifier, the AD524 does not require any exter-
nal components for fixed gains of 1, 10, 100 and 1000. For other
gain settings between 1 and 1000, only a single resistor is required.
The AD524 input is fully protected for both power-on and
power-off fault conditions.
The AD524 IC instrumentation amplifier is available in four
different versions of accuracy and operating temperature range.
The economical A grade, the low drift B grade, and lower drift,
higher linearity C grade are specified from −25°C to +85°C.
The S grade guarantees performance to specification over the
extended temperature range −55°C to +125°C. The AD524 is
available in a 16-lead ceramic DIP, 16-lead SBDIP, 16-lead SOIC
wide packages, and 20-terminal leadless chip carrier.
PRODUCT HIGHLIGHTS
1.
The AD524 has guaranteed low offset voltage, offset
voltage drift, and low noise for precision high gain
applications.
The AD524 is functionally complete with pin program-
mable gains of 1, 10, 100, and 1000, and single resistor
programmable for any gain.
Input and output offset nulling terminals are provided for
very high precision applications and to minimize offset
voltage changes in gain ranging applications.
The AD524 is input protected for both power-on and
power-off fault conditions.
The AD524 offers superior dynamic performance with a
gain bandwidth product of 25 MHz, full power response of
75 kHz and a settling time of 15 μs to 0.01% of a 20 V step
(G = 100).
2.
3.
4.
5.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD524
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 8
Connection Diagrams .................................................................. 8
ESD Caution .................................................................................. 8
Typical Performance Characteristics ............................................. 9
Test Circuits ................................................................................. 14
Theory of Operation ...................................................................... 15
Input Protection.......................................................................... 15
Input Offset and Output Offset ................................................ 15
Gain .............................................................................................. 16
Input Bias Currents .................................................................... 17
Common-Mode Rejection ........................................................ 17
Grounding ................................................................................... 18
Sense Terminal............................................................................ 18
Reference Terminal .................................................................... 18
Programmable Gain ................................................................... 20
Autozero Circuits ....................................................................... 20
Error Budget Analysis ................................................................ 21
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 25
REVISION HISTORY
11/07—Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to General Description .................................................... 1
Changes to Figure 1 .......................................................................... 1
Changes to Figure 3 and Figure 4 Captions .................................. 8
Changes to Error Budget Analysis Section ................................. 21
Changes to Ordering Guide .......................................................... 25
4/99—Rev. D to Rev. E
Rev. F | Page 2 of 28
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