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3D2D8G72UB3369MSP-5C

Description
DDR DRAM, 128MX72, CMOS, PBGA208, BGA-208
Categorystorage    storage   
File Size235KB,2 Pages
Manufacturer3D PLUS
Download Datasheet Parametric View All

3D2D8G72UB3369MSP-5C Overview

DDR DRAM, 128MX72, CMOS, PBGA208, BGA-208

3D2D8G72UB3369MSP-5C Parametric

Parameter NameAttribute value
Nominal supply voltage (Vsup)1.8 V
access modeMULTI BANK PAGE BURST
memory density9663676416 bit
memory width72
organize128MX72
Memory IC TypeDDR DRAM
Operating modeSYNCHRONOUS
self refreshYES
technologyCMOS
Temperature levelMILITARY
Other featuresSELF REFRESH
Number of functions1
Number of ports1
word count134217728 words
character code128000000
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
JESD-30 codeR-PBGA-B208
width16 mm
length22 mm
Maximum seat height5.9 mm
encapsulated codeBGA
Terminal pitch1 mm
Package shapeRECTANGULAR
Package formGRID ARRAY
surface mountYES
Terminal formBALL
Terminal locationBOTTOM
Number of terminals208
Package body materialPLASTIC/EPOXY
Minimum operating temperature-55 °C
Maximum operating temperature125 °C
Is SamacsysN
Objectid1383342620
package instructionBGA,
Reach Compliance CodeUnknown
ECCN codeEAR99
MEMORY MODULE
DDR2 SDRam 128Mx72-BGA
3D2D8G72UB3369
DDR2 Synchronous Dynamic Ram
8Gbit DDR2 SDRam organized as 128Mx72, based on 128Mx16
MODULE
Pin Assignment (Top View)
BGA 208 - (11x19 - Pitch 1.00mm)
(TOP VIEW - VIEWED BY TRANSPARENCY)
Features
- Organized as 128Mx72
- Core supply voltage 1.8V +/- 0.1V
- I/O supply voltage 1.8V +/- 0.1V
- Jedec standard 1.8V I/0 (SSTL_18 compatible)
- Data rate = 400, 533, 667, 800 Mbps
- Differential data strobe per byte
- 4n-bit prefetch architecture
- DLL to align DQ and DQS transitions with CK
- 8 internal banks per die for concurrent operation
- Programmable CAS Latency
- Posted CAS Additive Latency
- Write Latency = Read Latency - 1
t
CK
- Programmable Burst Lengths: 4 or 8
- One Die Termination
- 208 leaded or lead-free balls - pitch 1,0mm
- Available Temperature Range :
0°C to + 70°C
-40°C to + 85°C
-55°C to +125°C
- Suitable for high reliability applications
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L MN P R T U VW
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
-
VCC
VSS
DQ35
DQ52
LDM3
DQ38
UDM3
VCC
VSS
VCC
2
VCC
VSS
NC
DQ51
DQ36
3
VSS
NC
NC
NC
DQ33
4
VCC
NC
NC
NC
NC
DQ43
DQ57
DQ46
A9
VCC
A8
5
VCC
NC
NC
NC
BA2
DQ59
UDM2
DQ62
VCC
VSS
VCC
6
VSS
NC
NC
NC
DNU
DNU
VSS
7
VCC
NC
NC
DQ50
DQ39
DQ55
DQ63
8
VCC
NC
DQ34
DQ53
LDQS2
DQ58
DQ56
9
VSS
NC
CK3
DQ37
10
VCC
VSS
#CK3
#CK2
11
VSS
VCC
VSS
CK2
DQ32
LDQS3 DQ48
DQ42
DQ40
LDM2 DQ49
DQ54
DQ44
A6
A0
A2
DQ60
DQ41
A10
A11
A4
#LDQS2 #LDQS3
DQ61
DQ45
VCC #UDQS2 DQ47 UDQS2 UDQS3 #
UDQS3
VSS
VREF
VSS
VCC
VSS
ODT
VCC
VSS
VCC
DQ30
UDM0
DQ27
A3
VCC
BA0
DQ14
DQ25
DQ11
A12
A1
A5
DQ9
DQ28
DQ17
DQ1
#WE
DQ65
DQ67
VSS
A13
BA1
A7
DQ12
DQ22
LDM0
DQ4
DQ19
DQ68
VSS
VCC
VCC
VSS
VCC
UDM1
DQ6
LDM1
DQ20
DQ3
VSS
VCC
VSS
#UDQS1
UDQS1 UDQS0 DQ15
#UDQS0
DQ13
DQ29
DQ8
DQ10
DQ24
DQ26
DQ31
DQ23
DQ7
DQ18
#RAS
#CS
VCC
#LDQS1 #LDQS0
DQ0
CK0
VSS
VCC
VSS
DQ16
#CK0
#CK1
VSS
VCC
LDQS1 LDQS0
DQ5
CK1
#CK4
VSS
DQ21
DQ2
CK4
VCC
#LDQS4
UDQS4
#UDQS4
LDQS4
#CAS
DQ66
VSS
DQ71
DQ64
DQ69
VCC
CKE
DQ70
LDM4
VCC
FUNCTIONAL BLOCK DIAGRAM
LDQS0/#LDQS0 - UDQS0/#UDQS0
LDM0/UDM0
LDQS1/#LDQS1 - UDQS1/#UDQS1
LDM1/UDM1
LDQS2/#LDQS2 - UDQS2/#UDQS2
LDM2/UDM2
General description
The 3D2D8G72UB3369 is a high-speed highly integrated
DDR2 Synchronous Dynamic Ram Memory.
It is organized with 4 chips of 2Gbit + 1 chip for ECC.
It is particularly well suited for use in high reliability, high
performance and high density system applications, such as
servers or workstations.
The 3D2D8G72UB3369 is
packaged in a 208 balls BGA
DQ00-15
DQ16-31
DQ32-47
DQ48-63
DQ64-71
#CS #WE
#RAS #CAS CKE
LDQS3/#LDQS3 - UDQS3/#UDQS3
LDM3/UDM3
LDQS4/#LDQS4 - UDQS4/#UDQS4
LDM4
CK0/#CK0
CK1/#CK1
CK2/#CK2
CK3/#CK3
CK4/#CK4
available with lead-free or leaded balls.
(All other signals are common to the five memories)
DDR Memory Module
BETELGEUSE
3D PLUS S.A. reserves the right to change or cancel products or specifications without notice
3DFP-0369-REV : 5 - NOVEMBER 2012
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