74LV08D,112 datasheet, PDF - EEWORLD Datasheet

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74LV08D,112: Descriptionlogic gates quad 2-input and; Categorylogic logic; File Size80KB，14 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LV08D,112 Overview

logic gates quad 2-input and

74LV08D,112 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconductor
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SOIC
package instruction	3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14
Contacts	14
Manufacturer packaging code	SOT108-1
Reach Compliance Code	compliant
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	8.65 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	AND GATE
MaximumI(ol)	0.006 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TUBE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	19 ns
propagation delay (tpd)	33 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm

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74LV08

Quad 2-input AND gate

Rev. 03 — 6 April 2009

Product data sheet

1. General description

The 74LV08 is a low-voltage Si-gate CMOS device that is pin and function compatible with

74HC08 and 74HCT08.

The 74LV08 provides a quad 2-input AND function.

2. Features

Wide operating voltage: 1.0 V to 5.5 V

Optimized for low voltage applications: 1.0 V to 3.6 V

Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

Typical output ground bounce < 0.8 V at V

= 3.3 V and T

amb

= 25

°C

Typical HIGH-level output voltage (V

) undershoot: > 2 V at V

= 3.3 V and

amb

= 25

°C

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and from

−40 °C

to +125

°C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range

74LV08N

74LV08D

74LV08DB

74LV08PW

−40 °C

to +125

°C

−40 °C

to +125

°C

−40 °C

to +125

°C

−40 °C

to +125

°C

Name

DIP14

SO14

SSOP14

TSSOP14

Description

plastic dual in-line package; 14 leads (300 mil)

plastic small outline package; 14 leads;

body width 3.9 mm

plastic shrink small outline package; 14 leads;

body width 5.3 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

Version

SOT27-1

SOT108-1

SOT337-1

SOT402-1

Type number

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