74LVC245AD,112 datasheet, PDF - EEWORLD Datasheet

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74LVC245AD,112: Descriptionbus transceivers 3.3V octal transcvr; Categorylogic logic; File Size137KB，18 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LVC245AD,112 Overview

bus transceivers 3.3V octal transcvr

74LVC245AD,112 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconductor
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SOP
package instruction	7.50 MM, PLASTIC, MS-013, SOT163-1, SOP-20
Contacts	20
Manufacturer packaging code	SOT163-1
Reach Compliance Code	compliant
Other features	WITH DIRECTION CONTROL
Control type	COMMON CONTROL
Counting direction	BIDIRECTIONAL
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G20
JESD-609 code	e4
length	12.8 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS TRANSCEIVER
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TUBE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	8 ns
propagation delay (tpd)	9.5 ns
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
translate	N/A
width	7.5 mm
Base Number Matches	1

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74LVC245A; 74LVCH245A

Octal bus transceiver; 3-state

Rev. 8 — 28 June 2013

Product data sheet

1. General description

The 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state bus

compatible outputs in both send and receive directions. The device features an output

enable (OE) input for easy cascading and a send/receive (DIR) input for direction control.

OE controls the outputs so that the buses are effectively isolated.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices in mixed

3.3 V and 5 V applications.

The 74LVCH245A bus hold on data inputs eliminates the need for external pull-up

resistors to hold unused inputs.

2. Features and benefits



5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low-power consumption

Direct interface with TTL levels

Inputs accept voltages up to 5.5 V

High-impedance when V

= 0 V

Bus hold on all data inputs (74LVCH245A only)

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C

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