Dual, 1-TO-1
Differential-to-LVCMOS Translator/Buffer
Data Sheet
83023I
G
ENERAL
D
ESCRIPTION
The 83023I is a dual, 1-to-1 Differential-to-LVCMOS
Translator/Fanout Buffer. The differential inputs can accept most
differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and
HCSL) and translate into two single-ended LVCMOS outputs.
The small 8-lead SOIC footprint makes this device ideal for use
in applications with limited board space.
Features
•
Two LVCMOS / LVTTL outputs
•
Two differential CLKx, nCLKx input pairs
•
CLK, nCLK pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 350MHz (typical)
•
Output skew: 60ps (maximum)
•
Part-to-part skew: 500ps (maximum)
•
Additive phase jitter, RMS: 0.14ps (typical)
•
Small 8 lead SOIC package saves board space
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
B
LOCK
D
IAGRAM
CLK0
nCLK0
CLK1
nCLK1
Q0
P
IN
A
SSIGNMENT
CLK0
nCLK0
nCLK1
CLK1
1
2
3
4
8
7
6
5
V
DD
Q0
Q1
GND
Q1
83023I
8-Lead SOIC
3.8mm x 4.8mm x 1.47mm package body
M Package
Top View
©2015 Integrated Device Technology, Inc
1
December 14, 2015
83023I Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8
Name
CLK0
nCLK0
nCLK1
CLK1
GND
Q1
Q0
V
DD
Input
Input
Input
Input
Power
Output
Output
Power
Type
Pullup
Pullup
Description
Inverting differential clock input.
Inverting differential clock input.
Power supply ground.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Positive supply pin.
Pulldown Non-inverting differential clock input.
Pulldown Non-inverting differential clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
= 3.6V
Test Conditions
Minimum
Typical
4
23
51
51
7
Maximum
Units
pF
pF
kΩ
kΩ
Ω
©2015 Integrated Device Technology, Inc
2
December 14, 2015
83023I Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Positive Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
20
Units
V
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Test Conditions
Minimum
2.6
0.5
Typical
Maximum
Units
V
V
NOTE 1: Outputs terminated with 50Ω to V
DD
/2. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
T
ABLE
3C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
Test Conditions
V
IN
= V
DD
= 3.6V
V
IN
= V
DD
= 3.6V
V
IN
= 0V, V
DD
= 3.6V
V
IN
= 0V, V
DD
= 3.6V
-150
-5
0.15
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
GND + 0.5
NOTE 1, 2
NOTE 1: For single-ended applications, the maximum input voltage for CLKx, nCLKx is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
©2015 Integrated Device Technology, Inc
3
December 14, 2015
83023I Data Sheet
T
ABLE
4. AC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
t
R
t
F
odc
Parameter
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise Time
Output Fall Time
Output Duty Cycle
100MHz, Integration Range
(637kHz-10MHz)
0.8V to 2V
0.8V to 2V
f
≤
166MHz
f > 166MHz
100
100
45
43
0.14
250
250
50
50
400
400
55
57
1.8
Test Conditions
Minimum
Typical
350
2.1
2.4
60
500
Maximum
Units
MHz
ns
ps
ps
ps
ps
ps
%
%
All parameters measured at f
MAX
unless noted otherwise. See Parameter Measurement Information.
NOTE 1: Measured from the differential input crossing point to V
DD
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DD
/2. Input clocks are phase aligned.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DD
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2015 Integrated Device Technology, Inc
4
December 14, 2015
83023I Data Sheet
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the fun-
damental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using
a Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in the
0
-10
-20
-30
-40
-50
-60
1Hz band to the power in the fundamental. When the required
offset is specified, the phase noise is called a
dBc
value, which
simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
@ 100MHz
(12kHz to 20MHz)
= 0.14ps typical
SSB P
HASE
N
OISE
dBc/H
Z
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher
than the noise floor of the device. This is illustrated above. The
device meets the noise floor of what is shown, but can actually
be lower. The phase noise is dependant on the input source and
measurement equipment.
©2015 Integrated Device Technology, Inc
5
December 14, 2015
京公网安备 11010802033920号
EEWORLD
