MAX9174EUB+T datasheet, PDF - EEWORLD Datasheet

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MAX9174EUB+T: Descriptionlvds interface IC 670mhz lvds-to-lvds & X-lvds 1:2 split; Categorylogic logic; File Size820KB，14 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Environmental Compliance

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MAX9174EUB+T Overview

lvds interface IC 670mhz lvds-to-lvds & X-lvds 1:2 split

MAX9174EUB+T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Maxim
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	10
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	6 weeks
Input adjustment	DIFFERENTIAL
JESD-30 code	S-PDSO-G10
JESD-609 code	e3
length	3 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	10
Actual output times	2
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	SQUARE
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	3.23 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.045 ns
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3 mm

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19-2827; Rev 1; 4/04

670MHz LVDS-to-LVDS and Anything-to-LVDS

1:2 Splitters

General Description

The MAX9174/MAX9175 are 670MHz, low-jitter, low-

skew 1:2 splitters ideal for protection switching, loop-

back, and clock and signal distribution. The devices

feature ultra-low 1.0ps

(RMS)

random jitter (max) that

ensures reliable operation in high-speed links that are

highly sensitive to timing errors.

The MAX9174 has a fail-safe LVDS input and LVDS out-

puts. The MAX9175 has an anything differential input

(CML/LVDS/LVPECL) and LVDS outputs. The outputs

can be put into high impedance using the power-down

inputs. The MAX9174 features a fail-safe circuit that dri-

ves the outputs high when the input is open, undriven

and shorted, or undriven and terminated. The MAX9175

has a bias circuit that forces the outputs high when the

input is open. The power-down inputs are compatible

with standard LVTTL/LVCMOS logic. The power-down

inputs tolerate undershoot of -1V and overshoot of V

+ 1V. The MAX9174/MAX9175 are available in 10-pin

µMAX and 10-lead thin QFN with exposed pad pack-

ages, and operate from a single +3.3V supply over the

-40°C to +85°C temperature range.

♦

1.0ps

(RMS)

Jitter (max) at 670MHz

♦

80ps

(P-P)

Jitter (max) at 800Mbps Data Rate

♦

+3.3V Supply

♦

LVDS Fail-Safe Inputs (MAX9174)

♦

Anything Input (MAX9175) Accepts Differential

CML/LVDS/LVPECL

♦

Power-Down Inputs Tolerate -1.0V and V

+ 1.0V

♦

Low-Power CMOS Design

♦

10-Lead µMAX and Thin QFN Packages

♦

-40°C to +85°C Operating Temperature Range

♦

Conform to ANSI TIA/EIA-644 LVDS Standard

♦

IEC 61000-4-2 Level 4 ESD Rating

Features

MAX9174/MAX9175

Ordering Information

PART

MAX9174EUB

MAX9174ETB*

MAX9175EUB

MAX9175ETB*

TEMP RANGE

-40°C to +85°C

PIN-PACKAGE

10 µMAX

10 Thin QFN-EP**

10 µMAX

10 Thin QFN-EP**

Applications

Protection Switching

Loopback

Clock Distribution

Functional Diagram and Pin Configurations appear at end

of data sheet.

*Future

product—contact factory for availability.

**EP

= Exposed paddle.

Typical Application Circuit

CLOCK DISTRIBUTION

ASIC

MAX9174

MAX9176

CLK IN

CLK1

ASIC

MAX9174

MAX9176

CLK IN

CLK2

________________________________________________________________

Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

MAX9174EUB+T Related Products

	MAX9174EUB+T	MAX9175EUB+T	LHL10683J
Description	lvds interface IC 670mhz lvds-to-lvds & X-lvds 1:2 split	lvds interface IC 670mhz lvds->lvds & X->lvds 1:2 splitter	RADIAL LEADED INDUCTORS
Is it lead-free?	Lead free	Lead free	-
Is it Rohs certified?	conform to	conform to	-
Maker	Maxim	Maxim	-
Parts packaging code	TSSOP	TSSOP	-
package instruction	TSSOP,	TSSOP,	-
Contacts	10	10	-
Reach Compliance Code	compliant	compli	-
ECCN code	EAR99	EAR99	-
Factory Lead Time	6 weeks	6 weeks	-
Input adjustment	DIFFERENTIAL	DIFFERENTIAL	-
JESD-30 code	S-PDSO-G10	S-PDSO-G10	-
JESD-609 code	e3	e3	-
length	3 mm	3 mm	-
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	CLOCK DRIVER	-
Humidity sensitivity level	1	1	-
Number of functions	1	1	-
Number of terminals	10	10	-
Actual output times	2	2	-
Maximum operating temperature	85 °C	85 °C	-
Minimum operating temperature	-40 °C	-40 °C	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	TSSOP	TSSOP	-
Package shape	SQUARE	SQUARE	-
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-
Peak Reflow Temperature (Celsius)	260	260	-
propagation delay (tpd)	3.23 ns	3.23 ns	-
Certification status	Not Qualified	Not Qualified	-
Same Edge Skew-Max（tskwd）	0.045 ns	0.045 ns	-
Maximum seat height	1.1 mm	1.1 mm	-
Maximum supply voltage (Vsup)	3.6 V	3.6 V	-
Minimum supply voltage (Vsup)	3 V	3 V	-
Nominal supply voltage (Vsup)	3.3 V	3.3 V	-
surface mount	YES	YES	-
technology	CMOS	CMOS	-
Temperature level	INDUSTRIAL	INDUSTRIAL	-
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)	-
Terminal form	GULL WING	GULL WING	-
Terminal pitch	0.5 mm	0.5 mm	-
Terminal location	DUAL	DUAL	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-
width	3 mm	3 mm	-

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