74LVC1G17GV,125 datasheet, PDF

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74LVC1G17GV,125: Descriptionbuffers & line drivers sngl schmtt-trig buf; Categorylogic logic; File Size363KB，21 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LVC1G17GV,125 Overview

buffers & line drivers sngl schmtt-trig buf

74LVC1G17GV,125 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconductor
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	TSOP
package instruction	TSSOP, TSOP5/6,.11,37
Contacts	5
Manufacturer packaging code	SOT753
Reach Compliance Code	compliant
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G5
JESD-609 code	e3
length	2.9 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUFFER
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of functions	1
Number of entries	1
Number of terminals	5
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSOP5/6,.11,37
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	7 ns
propagation delay (tpd)	14 ns
Certification status	Not Qualified
Schmitt trigger	YES
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.95 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	1.5 mm
Base Number Matches	1

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74LVC1G17

Single Schmitt trigger buffer

Rev. 10 — 29 June 2012

Product data sheet

1. General description

The 74LVC1G17 provides a buffer function with Schmitt trigger input. It is capable of

transforming slowly changing input signals into sharply defined outputs.

The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of

this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

2. Features and benefits



Wide supply voltage range from 1.65 V to 5.5 V



High noise immunity



Complies with JEDEC standard



JESD8-7 (1.65 V to 1.95 V)



JESD8-5 (2.3 V to 2.7 V)



JESD8B/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



24

mA output drive (V

= 3.0 V)



CMOS low power consumption



Latch-up performance exceeds 250 mA



Direct interface with TTL levels



Unlimited rise and fall times



Inputs accept voltages up to 5 V



Multiple package options



Specified from

40 C

to +85

C

and from

40 C

to +125

C

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