3D3523
MONOLITHIC MANCHESTER
ENCODER/DECODER
(SERIES 3D3523)
FEATURES
•
•
•
•
•
•
•
•
•
•
All-silicon, low-power CMOS technology
Encoder and decoder function independently
Encoder has buffered clock output
3.3V operation
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Maximum data rate:
50 MBaud
Data rate range:
±15%
Lock-in time:
1 bit
For mechanical dimensions, click
here
.
For package marking details, click
here
.
CIN
CEN
RX
COUT
DIN
RESB
GND
data
3
delay
devices,
inc.
PACKAGES
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
CBUF
LOOP
TXENB
DOUTB
TXB
TX
3D3523-xxx
DIP (.300)
3D3523G-xxx Gull Wing (.300)
3D3523D-xxx SOIC (.150)
FUNCTIONAL DESCRIPTION
The 3D3523 is a monolithic CMOS Manchester Encoder/Decoder combo
chip. The device uses bi-phase-level encoding to embed a clock signal
into a data stream for transmission across a communications link. In this
encoding mode, a logic one is represented by a high-to-low transition in
the center of the bit cell, while a logic zero is represented by a low-to-high
transition.
The Manchester encoder combines the clock (CIN) and data (DIN) into a
single bi-phase-level signal (TX). An inverted version of this signal (TXB) is
also available. The data baud rate (in MBaud) is equal to the input clock
frequency (in MHz). A replica of the clock input is also available (CBUF).
The encoder may be reset by setting the RESB input low; otherwise, it
should be left high. The TX and TXB signals may be disabled (high-Z) by
setting TXENB high. Similarly, CBUF may be disabled by setting CEN low.
Under most operating conditions, TX and TXB are always enabled, and
CBUF is not used. With this in mind, the 3D3523 provides internal pull-
down resistors on CEN and TXENB, so that most users can leave these
inputs uncommitted.
PIN DESCRIPTIONS
Encoder:
CIN
Clock Input
DIN
Data Input
RESB Reset
CEN
Clock buffer enable
TXENB Transmit enable
CBUF Buffered clock
TX,TXB Transmitted signal
Decoder:
RX
Received Signal
COUT Recovered Clock
DOUTB Recovered Data
Common:
LOOP Loop enable
VDD
+3.3 Volts
GND
Ground
The Manchester decoder accepts the embedded-clock signal at the RX input. The recovered clock and
data signals are presented on COUT and DOUTB, respectively, with the data signal inverted. The
operating baud rate (in MBaud) is specified by the dash number of the device. The input baud rate may
vary by as much as
±15%
from the nominal device baud rate without compromising the integrity of the
information received.
Because the decoder is not PLL-based, it does not require a long preamble in order to lock onto the
received signal. Rather, the device requires at most one bit cell before the data presented at the output is
valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise
turned off.
Normally, the encoder and decoder function independently. However, if the LOOP input is set high, the
encoded TX signal is fed back internally into the decoder and the RX input is ignored. This feature is
useful for diagnostics. The LOOP input has an internal pull-down resistor and may be left uncommitted if
this feature is not needed.
2006
Data Delay Devices
Doc #06006
5/8/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D3523
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D3523-0.5
3D3523-1
3D3523-5
3D3523-10
3D3523-20
3D3523-25
3D3523-50
NOTE:
DECODER BAUD RATE (MBaud)
Nominal
Minimum
Maximum
0.50
1.00
5.00
10.00
20.00
25.00
50.00
0.43
0.85
4.25
8.50
17.00
21.25
42.50
0.57
1.15
5.75
11.50
23.00
28.75
57.50
Any baud rate between 0.5 and 50 MBaud not shown is also available at no extra cost.
APPLICATION NOTES
ENCODER
The Manchester encoder subsystem samples the
data input at the rising edge of the input clock.
The sampled data is used in conjunction with the
clock rising and falling edges to generate the by-
phase level Manchester code.
The encoder employs the timing of the clock
rising and falling edges (duty cycle) to implement
the required coding scheme, as shown in Figure
1. To reduce the difference between the output
data high time and low time, it is essential that
the deviation of the input clock duty cycle from
50/50 be minimized.
The encoder presents at its outputs the true and
the complimented encoded data. The High-to-
Low time skew of the selected data output should
be budgeted by the user, as it relates to his
application, to satisfactorily estimate the
distortion of the transmitted data stream. Such an
estimate is very useful in determining the
functionality and margins of the data link, if a
Manchester decoder is used to decode the
received data.
RESET
(RESB)
(Left high for normal operation)
1/f
C
1
0
1
1
0
0
1
0
CLOCK
(CIN)
t
DS
DATA
(DIN)
t
DH
T
2H
T
2L
T
1H
T
1L
TRANSMIT
(TXB)
TRANSMIT
(TX)
1
0
1
1
0
0
1
0
Figure 1: Timing Diagram (Encoder)
Doc #06006
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
3D3523
APPLICATION NOTES (CONT’D)
DECODER
The Manchester decoder subsystem samples the
input at precise pre-selected intervals to retrieve
the data and to recover the clock from the
received data stream. Its architecture comprises
finely tuned delay elements and proprietary
circuitry which, in conjunction with other circuits,
implement the data decoding and clock recovery
function.
Typically, the encoded data transmitted from a
source arrives at the decoder corrupted. Such
corruption of the received data manifests itself as
jitter and/or pulse width distortion at the decoder
input. The instantaneous deviations from
nominal Baud Rate and/or Pulse Width (high or
low) adversely impact the data extraction and
clock recovery function if their published limits
are exceeded.
See Table 4, Allowed Baud
Rate/Duty Cycle.
The decoder, being a self-
timed device, is tolerant of frequency modulation
(jitter) present in the input data stream, provided
that the input data pulse width variations remain
within the allowable ranges.
The decoder presents at its outputs the decoded
data (inverted) and the recovered clock. The
decoded data is
valid at the rising edge of the
clock.
The clock recovery function operates in two
modes dictated by the input data stream bit
sequence. When a data bit is succeeded by its
inverse, the clock recovery circuit is engaged and
forces the clock output low for a time equal
to
one over twice the baud rate.
Otherwise, the
input is presented at the clock output unchanged,
shifted in time. Therefore, the clock duty cycle is
strongly dependent on the baud rate, as this will
affect the clock-high duration.
The clock output falling edge is not operated on
by the clock recovery circuitry. It, therefore,
preserves more accurately the clock frequency
information embedded in the transmitted data. It
can therefore be used, if desired, to retrieve clock
frequency information.
INPUT SIGNAL CHARACTERISTICS
The 3D3523 inputs
are CMOS compatible. The
user should assure him/herself that
the 50%
(of VDD) threshold is used when referring to all
timing, especially to the input clock duty cycle
(encoder) and the received data (decoder).
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry is strongly dependent
on power supply and temperature. The
monolithic 3D3523 Manchester encoder/decoder
utilizes novel and innovative compensation
circuitry to minimize timing variations induced by
fluctuations in power supply and/or temperature.
Nevertheless, optimum performance is achieved
by providing a stable power supply and a clean
ground plane, and by placing a bypass capacitor
(0.1uf typically) as close to the device as
possible.
ENCODED
RECEIVED
(RX)
0
1
0
1
1
0
0
1
t
C
t
CL
CLOCK
(CLK)
DATA
(DATB)
DECODED
t
CWL
t
CD
1
0
1
1
0
0
1
Figure 2: Timing Diagram (Decoder)
Doc #06006
5/8/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D3523
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-10
-55
MAX
7.0
V
DD
+0.3
10
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
Low Level Output Current
Output Rise & Fall Time
SYMBOL
I
DD
V
IH
V
IL
I
IH
I
IL
I
OH
I
OL
T
R
& T
F
MIN
2.0
1.0
1.0
1.0
-4.0
4.0
2
MAX
5
UNITS
mA
V
V
µA
µA
mA
mA
ns
NOTES
V
IH
= V
DD
V
IL
= 0V
V
DD
= 3.0V
V
OH
= 2.4V
V
DD
= 3.0V
V
OL
= 0.4V
C
LD
= 5 pf
*I
DD
(Dynamic) = 2 * C
LD
* V
DD
* F
where: C
LD
= Average capacitance load/pin (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V, except as noted)
PARAMETER
Input Baud Rate (Encoder)
Clock Frequency
Data set-up to clock rising
Data hold from clock rising
TX High-Low time skew
TXB High-Low time skew
TX - TXB High/Low time skew
Nominal Input Baud Rate (Decoder)
Allowed Input Baud Rate Deviation
Allowed Input Baud Rate Deviation
Allowed Input Baud Rate Deviation
Allowed Input Duty Cycle
Bit Cell Time
Input Data Edge to Clock Falling Edge
Clock Width Low
Clock Falling Edge to Data Transition
SYMBOL
MIN
TYP
f
BN
f
C
t
DS
t
DH
t
1H
- t
1L
t
2H
- t
2L
t
1H
- t
2L
f
BN
f
B
f
B
f
B
tc
t
CL
t
CWL
t
CD
MAX
50
50
3.5
0
-3.5
-2.0
-3.0
5
-0.15 f
BN
-0.05 f
BN
-0.03 f
BN
42.5
50.0
1000/f
B
0.75 tc
500/f
BN
4.0
3.5
2.0
3.0
50
0.15 f
BN
0.05 f
BN
0.03 f
BN
57.5
UNITS
MBaud
MHz
ns
ns
ns
ns
ns
MBaud
MBaud
MBaud
MBaud
%
ns
ns
ns
ns
NOTES
1
1
1
0C to 70C
25C, 3.3V
3.0V to 3.6V
-55C to 125C
3.0V to 3.6V
±2ns
or 5%
3.0
5.0
Notes: 1: Assumes a 50% duty cycle clock input
Doc #06006
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
3D3523
AUTOMATED TESTING - MONOLITHIC PRODUCTS
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
5.0V
±
0.1V
Input Pulse:
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PW
IN
= 1/(2*BAUD)
Period:
PER
IN
= 1/BAUD
OUTPUT:
R
load
:
C
load
:
Threshold:
10KΩ
±
10%
5pf
±
10%
1.5V (Rising & Falling)
Device
Under
Test
10KΩ
5pf
Digital
Scope
470Ω
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
WAVEFORM
GENERATOR
OUT
TRIG
IN
DEVICE UNDER
TEST (DUT)
OUT
IN
TRIG
DIGITAL SCOPE
Figure 3: Test Setup
PER
IN
PW
IN
t
RISE
INPUT
SIGNAL
2.4V
1.5V
0.6V
t
FALL
V
IH
2.4V
1.5V
0.6V
V
IL
t
PHL
t
PLH
OUTPUT
SIGNAL
1.5V
V
OH
1.5V
V
OL
Figure 4: Timing Diagram
Doc #06006
5/8/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
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