BU-65170/61580 AND BU-61585
MIL-STD-1553A/B NOTICE 2 RT
AND BC/RT/MT, ADVANCED
COMMUNICATION ENGINE (ACE)
Make sure the next
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has...
®
FEATURES
•
Fully Integrated MIL-STD-1553
Interface Terminal
•
Flexible Processor/Memory Interface
•
Standard 4K x 16 RAM and Optional
12K x 16 or 8K x 17 RAM Available
•
Optional RAM Parity Generation/
Checking
•
Automatic BC Retries
•
Programmable BC Gap Times
•
BC Frame Auto-Repeat
•
Flexible RT Data Buffering
•
Programmable
Illegalization
•
Selective Message Monitor
•
Simultaneous RT/Monitor Mode
DESCRIPTION
DDC's BU-65170, BU-61580 and BU-61585 Bus Controller / Remote
Terminal / Monitor Terminal (BC/RT/MT) Advanced Communication
Engine (ACE) terminals comprise a complete integrated interface
between a host processor and a MIL-STD-1553 A and B or STANAG
3838 bus.
The ACE series is packaged in a 1.9 -square-inch, 70-pin, low-profile,
cofired MultiChip Module (MCM) ceramic package that is well suited
for applications with stringent height requirements.
The BU-61585 ACE integrates dual transceiver, protocol, memory
management, processor interface logic, and a total of 12K words of
RAM in a choice of DIP or flat pack packages. The BU-61585 requires
+5 V power and either -15 V or -12 V power.
The BU-61585 internal RAM can be configured as 12K x 16 or 8K x
17. The 8K x 17 RAM feature provides capability for memory integrity
checking by implementing RAM parity generation and verification on
all accesses. To minimize board space and “glue” logic, the ACE pro-
vides ultimate flexibility in interfacing to a host processor and internal/
external RAM.
The advanced functional architecture of the ACE terminals provides
software compatibility to DDC's Advanced Integrated Multiplexer
(AIM) series hybrids, while incorporating a multiplicity of architectural
enhancements. It allows flexible operation while off-loading the host
processor, ensuring data sample consistency, and supports bulk data
transfers.The ACE hybrids may be operated at either 12 or 16 MHz.
Wire bond options allow for programmable RT address (hardwired is
standard) and external transmitter inhibit inputs.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
©
1992, 1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
SHARED
RAM
TRANSCEIVER
A
DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
ADDRESS BUS
ADDRESS
BUFFERS
TX/RX_A
*
CH. A
TX/RX_A
DATA
BUFFERS
D15-D0
PROCESSOR
DATA BUS
TX/RX_B
A15-A0
PROCESSOR
ADDRESS BUS
2
TRANSCEIVER
B
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
RTAD4-RTAD0, RTADP
INCMD
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
CH. B
TX/RX_B
RT ADDRESS
MISCELLANEOUS
BU-65170/61580/61585
T-6/09-0
FIGURE 1. ACE BLOCK DIAGRAM
TABLE 1. “ACE” SERIES SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
Logic +5V
Transceiver +5V
-15V
-12V
Logic
Voltage Input Range
RECEIVER
Differential Input Resistance
(BU-65170/61580/61585X1,
BU-65170/61580/61585X2)
(Notes 1-7)
(BU-65170/61580/61585X3,
BU-65170/61580/61585X6)
(Notes 1-7)
Differential Input Capacitance
(BU-65170/61580/61585X1,
BU-65170/61580/61585X2)
(Notes 1-7)
(BU-65170/61580/61585X3,
BU-65170/61580/61585X6)
(Notes 1-7)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
Direct Coupled Across 35
Ω,
Measured on Bus
Transformer Coupled Across
70
Ω,
Measured on Bus
•(BU-65170/61580/61585X1)
•(BU-65170/61580/61585X2,X3, X6)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
LOGIC
VIH
VIL
IIH (Vcc=5.5V, VIN=Vcc)
IIH (Vcc=5.5V, VIN=2.7V)
SSFLAG/EXT_TRIG
All Other Inputs
IIL (Vcc=5.5V, VIN=0.4V)
SSFLAG/EXT_TRIG
All Other Inputs
VOH (Vcc=4.5V, VIH=2.7V,
VIL=0.2V, IOH=max)
VOL (Vcc=4.5V, VIH=2.7V,
VIL=0.2V, IOL=max)
IOL
DB15-DB0, A15-A0, MEMOE/
ADDR_LAT, MEMWR/
ZEROWAIT, DTREQ/16/8,
DTACK/POLARITY_SEL
MIN
TYP
MAX
UNITS
TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)
PARAMETER
LOGIC (cont’d)
INCMD, INT MEMENA_OUT,
READYD, IOEN, TXA, TXA,
TXB, TXB, TX_INH_OUT_A,
TX_INH_OUT_B
,
IOH
DB15-DB0, A15-A0, MEMOE/
ADDR_LAT, MEMWR/
ZEROWAIT, DTREQ/16/8,
DTACK/POLARITY_SEL
INCMD, INT, MEMENA_OUT,
READYD, IOEN, TXA, TXA,
TXB, TXB, TX_INH_OUT_A,
TX_INH_OUT_B,
CI (Input Capacitance)
CIO (Bi-directional signal input
capacitance)
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
BU-65170/61580/61585X1
• +5V (Logic)
• +5V (Ch. A, Ch. B)
• -15V (Ch. A, Ch. B)
BU-65170/61580/61585X2
• +5V (Logic)
• +5V (Ch. A, Ch. B)
• -12V (Ch. A, Ch. B)
BU-65170/61580/61585X3,
BU-65170/61580/61585X6
• +5V (Logic)
• +5V (Ch. A, Ch. B)
Current Drain (Total Hybrid)
BU-65170/61580X1
• +5V (Logic, Ch. A, Ch. B)
• -15V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X2
• +5V (Logic, Ch. A, Ch. B)
• -12V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X3,
BU-65170/61580X6
• +5V (Logic, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X1
• +5V (Logic, Ch. A, Ch. B)
• -15V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
MIN
3.2
TYP
MAX
UNITS
mA
-0.3
-0.3
-18.0
-18.0
-0.3
7.0
7.0
0.3
0.3
Vcc+0.
3
V
V
V
V
V
-6.4
mA
11
2.5
kΩ
kΩ
-3.2
mA
50
50
pF
pF
10
5
0.200
0.860
10
pF
pF
Vp-p
Vpeak
4.5
5.0
5.5
4.5
5.0
5.5
-15.75 -15.0 -14.25
4.5
4.5
-12.6
4.5
4.75
5.0
5.0
-12.0
5.0
5.0
95
30
68
105
180
95
30
80
130
230
5.5
5.5
-11.4
5.5
5.25
190
60
108
160
255
190
60
120
185
305
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
6
7
9
Vp-p
20
18
-250
100
2.0
150
27
27
10
250
300
Vp-p
Vp-p
mVp-p,
diff
mV
nsec
V
V
µA
µA
µA
µA
µA
V
V
0.8
-10
-692
-346
-794
-397
2.4
10
-84
-42
-100
-50
116
222
328
540
105
30
68
105
180
160
265
370
580
240
60
108
160
255
mA
mA
mA
mA
mA
mA
mA
mA
mA
0.4
6.4
mA
Data Device Corporation
www.ddc-web.com
3
BU-65170/61580/61585
T-6/09-0
TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)
PARAMETER
BU-61585X2
• +5V (Logic, Ch. A, Ch. B)
• -12V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X3,
BU-61585X6
• +5V (Logic, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
POWER DISSIPATION
Total Hybrid
BU-65170/61580X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X3,
BU-65170/61580X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X3,
BU-61585X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
BU-65170/61580X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X3,
BU-65170/61580X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
MIN
TYP
105
30
80
130
230
MAX UNITS
240
60
120
185
305
mA
mA
mA
mA
mA
TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)
PARAMETER
BU-61585X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X3,
BU-61585X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
CLOCK INPUT
Frequency
Nominal Value (programmable)
• Default Mode
• Software Programmable Option
Long Term Tolerance
• 1553A Mode
• 1553B Mode
Short Term Tolerance, 1 second
• 1553A Mode
• 1553B Mode
Duty Cycle
• 16 MHz
• 12 MHz
1553 MESSAGE TIMING
Completion of CPU Write (BC Start)-
to-Start of Next Message
BC Intermessage Gap (Note 8)
BC/RT/MT Response Timeout (Note 9)
18.5 nominal
22.5 nominal
50.5 nominal
128.0 nominal
RT Response Timeout (Note 11)
Transmitter Watchdog Timeout
THERMAL
Thermal Resistance, Junction-to-Case,
Hottest Die (θJC)
BU-65170/61580/61585X1,
BU-65170/61580/61585X2,
BU-65170/61580/61585X3,
BU-65170/61580/61585X6
Storage Temperature
Lead Temperature (soldering, 10 sec.)
PHYSICAL CHARACTERISTICS
Size
BU-65170/61580/61585 S
BU-65170/61580/61585 V
MIN
TYP
0.335
0.600
0.860
1.385
0.290
0.590
0.890
1.490
0.18
0.42
0.66
1.14
MAX UNITS
0.68
1.06
1.45
2.23
0.59
0.92
1.36
2.16
0.28
0.51
0.75
1.22
W
W
W
W
W
W
W
W
W
W
W
W
126
232
338
550
170
275
380
590
mA
mA
mA
mA
0.850
1.195
1.450
1.975
0.835
1.135
1.435
2.035
0.64
0.93
1.22
1.81
0.900
1.245
1.500
2.025
0.885
1.185
1.485
2.085
0.69
0.98
1.27
1.86
0.335
0.600
0.860
1.385
0.290
0.590
0.890
1.490
0.18
0.42
0.66
1.14
1.85
2.25
2.72
3.52
1.67
2.10
2.59
3.46
0.88
1.11
1.33
1.97
2.10
2.50
2.97
3.77
1.92
2.35
2.84
3.71
0.93
1.16
1.38
2.02
0.68
1.06
1.45
2.23
0.59
0.92
1.36
2.16
0.28
0.51
0.75
1.22
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
16.0
12.0
0.01
0.1
0.001
0.01
33
40
2.5
9.5
17.5 18.5
21.5 22.5
49.5 50.5
127 129.5
4
668
19.5
23.5
51.5
131
7
67
60
MHz
MHz
%
%
%
%
%
%
µs
µs
µs
µs
µs
µs
µs
µs
6.99
-65
6.8
150
+300
°C/W
°C/W
°C
°C
1.9 X 1.0 X 0.165
(48.3 x 25.4 x 4.19)
1.9 X 1.0 X 0.150
(48.3 x 25.4 x 3.81)
0.6 (17)
in.
(mm)
in.
(mm)
oz (g)
Weight
BU-65170/61580/61585 S/V
Data Device Corporation
www.ddc-web.com
4
BU-65170/61580/61585
T-6/09-0
Notes for Table 1: Notes 1 through 6 are applicable to the Receiver
Differential Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Measurement of impedance is directly between pins TX/RX A(B)
and TX/RX A(B) of the BU-65170/61580XX hybrid.
(3) Assuming the connection of all power and ground inputs to the
hybrid.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and Typical capacitance parameters are
guaranteed,but not tested, over the operating range.
(7) Assumes a common mode voltage within the frequency range of dc
to 2MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), referenced to hybrid
ground. Use a DDC recommended transformer or other transformer
that provides an equivalent minimum CMRR.
(8) Typical value for minimum intermessage gap time. Under software
control, may be lengthened to (65,535µs minus message time), in
increments of 1µs.
(9) Software programmable (4 options). Includes RT-to-RT Timeout
(Mid-Parity of Transmit Command to Mid-Sync of Transmitting RT
Status).
(10) For both +5V logic and transceiver. +5V for channels A and B.
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12) Specifications for BU-65171, BU-61581, and BU-61586 are identi-
cal to the specifications for the BU-65170, BU-61580, and
BU-61585 respectively.
The memory management scheme for RT mode provides an
option for separation of broadcast data, in compliance with
1553B Notice 2. Both double buffer and circular buffer options
are programmable by subaddress. These features serve to
ensure data consistency and to off-load the host processor for
bulk data transfer applications.
The ACE series implements three monitor modes: a word moni-
tor, a selective message monitor, and a combined RT/selective
monitor. Other features include options for automatic retries and
programmable intermessage gap for BC mode, an internal Time
Tag Register, an Interrupt Status Register and internal command
illegalization for RT mode.
FUNCTIONAL OVERVIEW
TRANSCEIVERS
INTRODUCTION
DDC's ACE series of Integrated BC/RT/MT hybrids provide a
complete, flexible interface between a microprocessor and a
MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus,
implementing Bus Controller, Remote Terminal (RT) and Monitor
Terminal (MT) modes. Packaged in a single 1.9-square-inch,
70-pin DIP or surface mountable flatpack or J-lead package, the
ACE series contains dual low-power transceivers and encoder/
decoders, complete BC/RT/MT multi-protocol logic, memory
management and interrupt logic, 4K x 16 of shared static RAM
and a direct, buffered interface to a host processor bus.
The BU-65170/61580 contains internal address latches and bidi-
rectional data buffers to provide a direct interface to a host pro-
cessor bus. The BU-65170/61580 may be interfaced directly to
both 16-bit and 8-bit microprocessors in a buffered shared RAM
configuration. In addition, the ACE may connect to a 16-bit pro-
cessor bus via a Direct Memory Access (DMA) interface. The
BU-65170/61580 includes 4K words of buffered RAM.
Alternatively, the ACE may be interfaced to as much as 64K
words of external RAM in either the shared RAM or DMA con-
figurations.
The ACE RT mode is multiprotocol, supporting MIL-STD-1553A,
MIL-STD-1553B Notice 2, STANAG 3838 (including EFAbus),
and the McAir A3818, A5232, and A5690 protocols. Full compli-
ance to the McAir specs, however, requires the use of a sinusoi-
dal transceiver (transceiver option 5). Refer to the BU-61590
data sheet for additional information on McAir terminals.
Data Device Corporation
www.ddc-web.com
The transceivers in the BU-65170/61580X3(X6) are fully mono-
lithic, requiring only a +5 volt power input. Besides eliminating
the need for an additional power supply, the use of a 5 volt (only)
transceiver requires the use of step-up, rather than step-down,
isolation transformers. This provides the advantage of a higher
terminal input impedance than is possible for a 15 volt or 12 volt
transmitter. As a result, there is greater margin for the input
impedance test, mandated for 1553 validation testing. This
allows for longer cable lengths between an LRU's system con-
nector and the isolation transformers of an embedded 1553 ter-
minal.
For the +5 V and -15 V/-12 V front end, the BU-65170/
61580X1(X2) uses low-power bipolar analog monolithic and
thick-film hybrid technology. The transceiver requires +5 V and
-15 V (-12 V) only (requiring no +15 V/+12 V) and includes volt-
age source transmitters. The voltage source transmitters provide
superior line driving capability for long cables and heavy amounts
of bus loading. In addition, the monolithic transceivers in the
BU-65170/61580X1 provide a minimum stub voltage level of 20
volts peak-to-peak transformer coupled, making them suitable
for MIL-STD-1760 applications.
The receiver sections of the BU-65170/61580 are fully compliant
with MIL-STD-1553B in terms of front end overvoltage protec-
tion, threshold, common mode rejection, and word error rate. In
addition, the receiver filters have been designed for optimal
operation with the J´ chip's Manchester II decoders.
J´ DIGITAL MONOLITHIC
The J´ digital monolithic represents the cornerstone element of
the ACE family of terminals. The development of the J´ chip rep-
resents the fifth generation of 1553 protocol and interface design
for DDC. Over the years, DDC's 1553 protocol and interface
design has evolved from: (1) discrete component sets, consisting
of multiple hybrids (with large numbers of chips inside the indi-
vidual hybrids) and programmable logic devices, to (2) multiple
custom ASICs to perform the functions of encoder/decoder and
BU-65170/61580/61585
T-6/09-0
5
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