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®
BU-6474X/6484X/6486X
MINI-ACE
®
MARK3/MICRO-ACE
®
*-TE
FEATURES
•
Fully Integrated 3.3 or 5.0 Volt, 1553
A/B Notice 2 Terminal
•
World’s First all 3.3 Volt Terminal
•
Transceiver Power-Down Options
•
World’s Smallest CQFP MIL-STD-1553
Device
•
80-pin Ceramic Flat/Gull Wing
Package or 324-Ball BGA Package
•
Enhanced Mini-ACE Architecture
•
Multiple Configurations:
- RT-only, 4K RAM
- BC/RT/Monitor, 4K RAM
DESCRIPTION
The Mini-ACE Mark3 and Micro-ACE-TE are the world's first MIL-STD-1553
terminals which can be powered entirely by +3.3 volts, thus eliminating the
need for a +5 volt power supply. With a package body of 0.880 inches square
and a gull wing "toe-to-toe" dimension of 1.110 inches, the Mini-ACE Mark3
is the industry's smallest ceramic gull-lead 1553 terminal. At 0.815 inches
square, the Micro-ACE-TE (BGA package) provides the smallest industry
footprint, enabling its use in applications where PC board space is at a pre-
mium.
These devices integrate dual 3.3 or 5 volt transceivers, 3.3 or 5.0 volt protocol
logic, and either 4K or 64K words of internal RAM. The architecture is identi-
cal to that of the Enhanced Mini-ACE, and most features are functionally and
software compatible with the previous Mini-ACE (Plus) and ACE genera-
tions.
A salient feature of the Mini-ACE Mark3 and Micro-ACE-TE is the advanced
bus controller architecture. This provides methods to control message sched-
uling, the means to minimize host overhead for asynchronous message
insertion, facilitate bulk data transfers and double buffering, and support
various message retry and bus switching strategies.
The remote terminal architecture provides flexibility in meeting all common
MIL-STD-1553 protocols. The choice of RT data buffering and interrupt
options provides robust support for synchronous and asynchronous messag-
ing, while ensuring data sample consistency and supporting bulk data trans-
fers. The monitor mode provides true message monitoring, and supports fil-
tering on an RT address/T-R bit/subaddress basis.
The Mini-ACE Mark3 and Micro-ACE-TE incorporate fully autonomous built-
in self-tests of internal protocol logic and RAM. The terminals provide
the
same flexibility in host interface configurations as the ACE/Mini-ACE, along
with a reduction in the host processor's worst case holdoff time.
- BC/RT/Monitor, 64K RAM
•
Supports 1553A/B Notice 2, McAir,
STANAG 3838 Protocols
•
MIL-STD-1553, McAir, and MIL-
STD-1760 Transceiver Options
•
Highly Flexible Host Side Interface
•
Compatible With Mini-ACE and ACE
Generations
•
Highly Autonomous BC with Built-In
Message Sequence Controller
•
Choice of Single, Double, and
Circular RT Buffering Options
•
Selective Message Monitor
•
Comprehensive Built-In Self-Test
•
Choice Of 10, 12, 16, or 20 MHz Clock
Inputs
•
Software Libraries and Drivers
available for Windows® 9x/2000/XP,
Windows NT®, VxWorks® and Linux
•
Available with Full Military
Temperature Range and Screening
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
subject to one or more patents pending.
All trademarks are the property of their respective owners.
© 2002 Data Device Corporation
*
The technology used in DDC’s Micro-ACE series of products may be
Vcc
SHARED
RAM
(1)
TRANSCEIVER
A
DATA BUS
D15-D0
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
ADDRESS BUS
ADDRESS
BUFFERS
DATA
BUFFERS
PROCESSOR
DATA BUS
TX/RX_A
Data Device Corporation
www.ddc-web.com
A15-A0
PROCESSOR
ADDRESS BUS
TRANSCEIVER
B
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
INCMD/MCRST
CLK_IN, TAG_CLK,
MSTCLR, SSFLAG/EXT_TRG, TX-INH_A, TX-INH_B,
SLEEPIN/UPADDREN
(1:2.038)
CH. A
(Note 2)
TX/RX_A
TX/RX_B
(1:2.038)
CH. B
(Note 2)
2
TX/RX_B
RT ADDRESS
RTAD4-RTAD0, RTADP, RTADD_LAT
MISCELLANEOUS
BU-6474X/6484X/6486X
AJ-6/11-0
Notes:
1. See Ordering Information for Available Memory Options.
2. Transformer-coupled configuration and ratio shown.
FIGURE 1. MINI-ACE MARK3 AND MICRO-ACE-TE BLOCK DIAGRAM
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage (Note 12)
•
Logic +5V
•
Logic +3.3V
•
RAM +5V
•
Transceivers +5V
•
Transceivers +3.3V
(not during transmit)
•
Transceivers +3.3V
(during transmit)
Logic
•
+5V Logic Input Range
•
+3.3V Logic Input Range
RECEIVER
Differential Input Resistance
(Notes 1-6)
+5.0V
+3.3V
Differential Input Capacitance
(Notes 1-6)
+5.0V
+3.3V
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common-Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
•
Direct Coupled Across 35
Ω,
Measured on Bus
•
Transformer Coupled Across
70
Ω,
Measured on Bus
BU-64XXXXX-XX0
BU-64XXXXX-XX2 (Note 13)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70
Ω
Rise/Fall Time
BU-64XXXX8/3
BU-64XXXX9/4
LOGIC
V
IH
All signals except CLK_IN
CLK_IN
V
IL
All signals except CLK_IN
CLK_IN
Schmidt Hysteresis
All signals except CLK_IN
CLK_IN
I
IH,
I
IL
All signals except CLK_IN
I
IH
(Vcc=3.6V, V
IN
=Vcc)
I
IH
(Vcc=3.6V, V
IN
=2.7V)
I
IL
(Vcc=3.6V, V
IN
=0.4V)
I
IH,
I
IL
All signals except CLK_IN
I
IH
(Vcc=5.25V, Vin=Vcc)
I
IH
(Vcc=5.25V, I
IH
Vin=2.7V)
I
IL
(Vcc=5.25V, Vin=0.4V)
0.4
1.0
MIN
TYP
MAX
UNITS
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
PARAMETER
LOGIC (CONT.)
V
OH
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OH
=max)
V
OL
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
V
OH
(Vcc=4.5V, V
IH
=2.7V,
V
IL
=0.2V, I
OH
=max)
V
OL
(Vcc=4.5V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
CLK_IN
I
IH
I
IL
I
OL
(Vcc = 4.5V)
I
OH
(Vcc = 4.5V)
MIN
TYP
MAX
UNITS
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
6.0
4.1
6.0
7.0
6.0
4.5
6.0
6.0
V
V
V
V
V
V
V
V
2.4
0.4
2.4
0.4
-10
-10
3.4
-3.4
2.2
-2.2
50
50
10
10
V
V
V
V
µA
µA
mA
mA
mA
mA
pF
pF
2.5
2.0
25
40
0.860
10
kΩ
kΩ
pF
pF
Vp-p
Vpeak
I
OL
(Vcc = 3.0V)
I
OH
(Vcc = 3.0V)
C
I
(Input Capacitance)
C
IO
(Bi-directional signal input
capacitance)
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances (Note 12)
•
Logic +3.3V
•
Logic +5.0V
•
RAM +5.0V
•
Transceivers +3.3V
•
Transceivers +5.0V
Current Drain (Total Hybrid) (Note 14)
BU-64743X8/9-XX0,
BU-64843X8/9-XX0 (1553&McAir)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743F/G3/4-XX0,
BU-64843F/G3/4-XX0 (1553&McAir)
+5V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic)
BU-64745F/G3/4-XX0
BU-64845F/G3/4-XX0 (1553&McAir)
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64745F/G3-XX2
BU-64845F/G3-XX2 (1760)
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64863X8/9-XX0 (1553&McAir)
• Idle w/ transceiver SLEEPIN enabled
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
0.200
6
7
9
Vp-p
3.00
4.5
4.5
3.14
4.75
3.3
5.0
5.0
3.3
5.0
3.60
5.5
5.5
3.46
5.25
V
V
V
V
V
18
20
-250
100
200
20
21.5
27
27
10
250
Vp-p
Vp-p
mVp-p
mVp
nsec
nsec
56
246
436
816
95
300
500
900
mA
mA
mA
mA
150
250
300
300
2.1
0.8•V
cc
0.7
0.2•Vcc
V
V
V
V
V
V
65
169
273
481
25
100
205
310
520
40
mA
mA
mA
mA
mA
116
222
328
540
160
265
370
580
mA
mA
mA
mA
-10
-350
-350
10
-33
-33
µA
µA
µA
116
233
350
584
31
77
267
457
837
160
276
392
625
69
110
315
515
915
mA
mA
mA
mA
mA
mA
mA
mA
mA
-10
-350
-350
10
-50
-50
µA
µA
µA
Data Device Corporation
www.ddc-web.com
3
BU-6474X/6484X/6486X
AJ-6/11-0
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
PARAMETER
POWER SUPPLY REQUIREMENTS
(CONT.)
BU-64863F/G3/4-XX0 (1553&McAir)
+5V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic, 64K RAM)
BU-64743X8-XX2,
BU-64843X8-XX2 (1760)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743F/G3-XX2,
BU-64843F/G3-XX2 (1760)
+5V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic)
BU-64840B3-X02 (1760)
+5V (Logic, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64840B3-X02 (1760)
+5V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic)
BU-64863X8-XX2 (1760)
• Idle w/ transceiver SLEEPIN enabled
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64863F/G3-XX2 (1760)
+5V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic, 64K RAM)
BU-64860B(R)3-X02 (1760)
+5V (Logic, 64K RAM, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64860B(R)3-X02 (1760)
+5V (64K RAM, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
• +3.3V (Logic)
BU-64743X0-XX0,
BU-64843X0-XX0 (Xcvrless)
BU-64863X0-XX0 (Xcvrless)
MIN
TYP
MAX
UNITS
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
PARAMETER
POWER DISSIPATION
TOTAL HYBRID (NOTES 14 AND 15)
BU-64743X8/9-XX0,
BU-64843X8/9-XX0 (1553&McAir)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743F/G3/4-XX0,
BU-64843F/G3/4-XX0 (1553&McAir)
+3.3V (Logic) +5.0V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64745F/G3/4-XX0
BU-64845F/G3/4-XX0 (1553&McAir)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64745F/G3-XX2
BU-64845F/G3-XX2 (1760)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64863X8/9-XX0 (1553&McAir)
• Idle w/ transceiver SLEEPIN enabled
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64863F/G3/4-XX0 (1553&McAir)
+3.3V (Logic, 64K RAM) +5.0V (Ch.
A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743X8-XX2,
BU-64843X8-XX2 (1760)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743F/G3-XX2,
BU-64843F/G3-XX2 (1760)
+3.3V (Logic) +5.0V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64840B3-X02 (1760)
+5.0V (Logic, Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64840B3-X02 (1760)
+3.3V (Logic) +5.0V (Ch. A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
MIN
TYP
MAX
UNITS
65
169
273
481
21
55
216
377
699
100
205
310
520
55
95
315
535
975
mA
mA
mA
mA
mA
mA
mA
mA
mA
0.18
0.57
0.91
1.58
0.31
0.69
1.04
1.74
W
W
W
W
0.41
0.70
0.94
1.40
0.64
0.93
1.22
1.81
0.64
0.99
1.34
2.04
0.10
0.25
0.62
0.97
1.64
0.63
0.85
1.07
1.51
0.88
1.11
1.33
1.97
0.88
1.17
1.46
2.05
0.23
0.36
0.73
1.09
1.79
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
65
180
295
525
25
116
233
350
584
65
180
295
525
25
27
76
237
398
720
65
180
295
525
21
116
228
340
563
66
174
282
498
25
25
21
100
216
332
565
40
160
276
392
625
100
216
332
565
40
69
110
330
550
990
100
216
332
565
55
180
296
412
645
120
236
352
585
40
40
55
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
0.44
0.74
0.99
1.44
0.18
0.49
0.76
1.31
0.68
0.90
1.12
1.56
0.31
0.71
1.08
1.83
W
W
W
W
W
W
W
W
0.41
0.72
0.97
1.45
0.58
0.87
1.13
1.62
0.41
0.72
0.97
1.45
0.63
0.86
1.09
1.56
0.80
1.03
1.26
1.73
0.63
0.86
1.09
1.56
W
W
W
W
W
W
W
W
W
W
W
W
Data Device Corporation
www.ddc-web.com
4
BU-6474X/6484X/6486X
AJ-6/11-0
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
PARAMETER
POWER DISSIPATION (CONT)
TOTAL HYBRID (NOTES 14 AND 15)
BU-64863X8-XX2 (1760)
• Idle w/ transceiver SLEEPIN enabled
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64863F/G3-XX2 (1760)
+3.3V (Logic, 64K RAM) +5.0V (Ch.
A, Ch. B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64860B(R)3-X02 (1760)
+5.0V (Logic, Ch. A, Ch. B, 64K RAM)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64860B(R)3-X02 (1760)
+3.3V (Logic) +5.0V (Ch. A, Ch. B,
64K RAM)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64743X0-XX0, BU-64843X0-XX0
(Xcvrless)
BU-64863X0-XX0 (Xcvrless)
HOTTEST DIE
BU-64XXXX8/9-XX0 (1553&McAir)
• Idle w/ transceiver SLEEPIN enabled
(BU-64863 only)
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64XXXX3/4-XX0 (1553&McAir)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64XXXX8-XX2 (1760)
• Idle w/ transceiver SLEEPIN enabled
(BU-64863 only)
• Idle w/ transceiver SLEEPIN disabled
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64XXXX3-XX2 (1760)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-64XX3X0-XX0 (Xcvrless)
CLOCK INPUT
• Frequency:
Nominal Values
Default Mode
Option
Option
Option
MIN
TYP
MAX
UNITS
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
PARAMETER
CLOCK INPUT (CONT)
• Long Term Tolerance
1553A Compliance
1553B Compliance
• Short Term Tolerance, 1 second
1553A Compliance
1553B Compliance
Duty Cycle
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of First Message for
Non-enhanced BC Mode
BC Intermessage Gap (Note 8)
Non-enhanced (Mini-ACE compatible)
BC mode
Enhanced BC mode (Note 9)
BC/RT/MT Response Timeout (Note 10)
• 18.5 nominal
• 22.5 nominal
• 50.5 nominal
• 128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
THERMAL
FLAT PACK/GULL WING
80-pin Ceramic Package
Thermal Resistance,
Junction-to-Case, Hottest Die (θ
JC
) Note 16
MICRO-ACE-TE BGA
324-ball BGA Package
(see Thermal Management section)
Junction-to-Balls, Hottest Die (θ
JB
)
ALL PACKAGES
Operating Case/Ball Temperature
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
-EXX
Storage Temperature
SOLDERING/MOUNTING
FLAT PACK/GULL WING
Lead Temperature (soldering, 10 sec.)
324-BALL BGA PACKAGE
The reflow profile detailed in IPC/
JEDEC J-STD-020 is applicable for
both leaded and lead-free products
17.5
21.5
49.5
127
4
660.5
MIN
TYP
MAX UNITS
0.09
0.25
0.53
0.93
1.36
0.23
0.36
0.74
1.12
1.87
W
W
W
W
W
0.01
0.10
-0.001
-0.01
40
-0.01
-0.10
0.001
0.01
60
%
%
%
%
%
0.44
0.76
1.01
1.50
0.64
0.87
1.12
1.60
0.68
0.91
1.14
1.61
0.90
1.13
1.36
1.83
W
W
W
W
W
W
W
W
2.5
µs
9.5
10 to
10.5
18.0 19.5
22.5 23.5
50.5 51.5
129.5 131
7
µs
µs
µs
µs
µs
µs
µs
µs
0.40
0.71
0.95
1.41
0.08
0.07
0.01
0.05
0.39
0.72
1.38
0.16
0.39
0.61
1.06
0.01
0.05
0.39
0.60
1.15
0.16
0.40
0.63
1.11
0.08
0.73
0.96
1.19
1.66
0.132
0.182
0.02
0.09
0.47
0.82
1.52
0.25
0.47
0.69
1.13
0.02
0.09
0.49
0.85
1.61
0.25
0.48
0.71
1.18
0.13
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
9
11
°C/W
15
°C/W
-55
-40
0
-40
-65
+125
+85
+70
+100
+150
°C
°C
°C
°C
°C
+300
°C
Refer to DDC’s Application Note #A/N49 “BGA User’s
Guide” for additional important mounting information.
+245
°C
PHYSICAL CHARACTERISTICS
Package Body Size
80-pin Ceramic Flat pack or Gull Wing
324-ball BGA
Micro-ACE-TE
Moisture Sensitivity Level
Electrostatic Discharge Sensitivity
Lead Toe-to-Toe Distance
80-pin Gull Wing
See next page for TABLE 1 notes.
0.880 X 0.880 X 0.13
(22.35 X 22.35 X 3.3)
0.815 X 0.815 X 0.12
(20.7 X 20.7 X 3.05)
MSL-3
ESD Class 0
1.110
(28.194)
in.
(mm)
in.
(mm)
16.0
12.0
10.0
20.0
MHz
MHz
MHz
MHz
in.
(mm)
Data Device Corporation
www.ddc-web.com
5
BU-6474X/6484X/6486X
AJ-6/11-0
FPGA/CPLD
京公网安备 11010802033920号
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