BU-65843F3-802 datasheet, PDF - EEWORLD Datasheet

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BU-65843F3-802: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP80, 0.890 X 0.890 INCH, 0.130 INCH HEIGHT, CERAMIC, QFP-80; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，79 Pages; ManufacturerData Device Corporation

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BU-65843F3-802 Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP80, 0.890 X 0.890 INCH, 0.130 INCH HEIGHT, CERAMIC, QFP-80

BU-65843F3-802 Parametric

Parameter Name	Attribute value
Terminal location	QUAD
Number of terminals	80
encapsulated code	QFF
Encapsulate equivalent code	QFL80,.89SQ,40
Package shape	SQUARE
Terminal form	FLAT
Terminal pitch	1.016 mm
Package body material	CERAMIC, METAL-SEALED COFIRED
Package form	FLATPACK
Terminal surface	Tin/Lead (Sn/Pb)
Maximum operating temperature	70 °C
Minimum operating temperature
Is it Rohs certified?	No
Reach Compliance Code	Compliant
Country Of Origin	Taiwan, USA
Is Samacsys	N
YTEOL	7
Objectid	1154996292
package instruction	QFF, QFL80,.89SQ,40
boundary scan	YES
Data encoding/decoding methods	BIPH-LEVEL (MANCHESTER)
Number of serial I/Os	2
Minimum supply voltage	4.75 V
Other features	LG-MAX; WD-MAX
low power mode	YES
Maximum supply voltage	5.5 V
technology	CMOS
Temperature level	COMMERCIAL
letter of agreement	MIL STD 1553A; MIL STD 1553B; MIL STD 1760; STANAG 3838
Address bus width	32
Bus compatibility	PCI
maximum clock frequency	33.3 MHz
Maximum data transfer rate	1 MBps
External data bus width	32
Nominal supply voltage	5 V
surface mount	YES
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
JESD-30 code	S-CQFP-F80
JESD-609 code	e0
Certification status	Not Qualified
Maximum seat height	3.302 mm
width	22.606 mm
length	22.606 mm

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PCI MICRO-ACE

*-TE

BU-65743/65843/65863/65864

PCI MINI-ACE

MARK3 AND

FEATURES

Make sure the next

Card you purchase

has...

•

32-Bit/33MHz, 3.3Volt, PCI Target

Interface

•

Fully Integrated 1553A/B Notice 2,

1760, McAir, STANAG 3838 Interface

Terminal

•

All +3.3V Operation or +3.3V Logic

and +5V Transceivers

•

0.88 inch square, 80-Pin CQFP (PCI

Mini-ACE Mark3) or 0.80 inch square

324 ball BGA (PCI Micro-ACE TE)

•

Compatible with PCI Enhanced Mini-

ACE, Enhanced Mini-ACE, Mini-ACE

and ACE Generations

•

Choice of :

RT only with 4K RAM (BU-65743)

- BC/RT/MT with 4K RAM (BU-65843)

- BC/RT/MT with 64K RAM, and RAM

Parity (BU-65863, BU-65864)

•

Sleep Mode Option

•

Choice of 10, 12, 16, or 20 MHz 1553

Clock

•

Highly Autonomous BC with Built-In

Message Sequence Control:

- Frame Scheduling

- Branching

- Asynchronous Message Insertion

- General Purpose Queue

- User-defined Interrupts

•

Advanced RT Functions

- Global Circular Buffering

- Interrupt Status Queue

- 50% Circular Buffer Rollover

Interrupts

•

Selective Message Monitor or

RT/Monitor

FOR MORE INFORMATION CONTACT:

DESCRIPTION

The PCI Mini-ACE Mark3/Micro-ACE TE family of MIL-STD-1553 terminals

provides a complete interface between a 32-Bit/33Mhz 3.3V signaling PCI Bus

and a MIL-STD-1553 bus. These terminals integrate dual transceiver, protocol

logic, and 4K or 64K words of RAM, all of which can be powered from 3.3V.

With a 0.88-inch square package, the PCI Mini-ACE Mark3 is the smallest

ceramic CQFP PCI 1553 solution available. The 0.80-inch square 324 ball BGA

PCI Micro-ACE TE has an even smaller footprint, but has a more restricted

operating temperature range. Both are 100% software compatible with the

larger PCI Enhanced Mini-ACE and add TAG_CLK inputs. The TAG_CLK input

allows a software selectable external time tag clock input. Both parts are avail-

able with a choice of either 3.3V transceivers or 5V transceivers.

The PCI Micro-ACE TE has a more restricted set of options compared to the

PCI Mini-ACE Mark3. Please consult the ordering information at the rear of the

data sheet to see which options are available. In addition, the PCI Micro-ACE

TE adds RTBOOT and 1553 clock select inputs for applications which must

boot into RT mode with Busy bit set.

The PCI Mini-ACE Mark3/Micro-ACE TE is nearly 100% software compatible

with the Enhanced Mini-ACE and previous generation Mini-ACE terminals. The

PCI interface to this terminal is not 5V tolerant.

Multiprotocol support of MIL-STD-1553A/B and STANAG 3838, including

Mark3 versions incorporating McAir compatible transmitters, is provided. There

is a choice of 10, 12, 16, or 20 MHz 1553 clocks. The BC/RT/MT versions with

64K words of RAM include built-in RAM parity checking.

BC features include a built-in message sequence control engine, with a set of

20 instructions. This provides an autonomous means of implementing multi-

frame message scheduling, message retry schemes, data double buffering,

asynchronous message insertion, and reporting to the host CPU.

The PCI Mini-ACE Mark3 and Micro-ACE TE RT offer single and circular sub-

address buffering schemes, along with a global circular buffering option, 50%

rollover interrupt for circular buffers, and an interrupt status queue.

FOR MORE INFORMATION CONTACT:

Technical Support:

1-800-DDC-5757 ext. 7771

Technical Support:

1-800-DDC-5757 ext. 7771

Data Device Corporation

105 Wilbur Place

Bohemia, New York 11716

631-567-5600 Fax: 631-567-7358

www.ddc-web.com

The technology used in DDC’s Micro-ACE series of products may be

subject to one or more patents pending.

All trademarks are the property of their respective owners.

2003 Data Device Corporation

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