BL1L5MT160ST1 datasheet, PDF - EEWORLD Datasheet

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BL1L5MT160ST1: DescriptionActive Delay Line, 1-Func, PBGA14, SMT-14; Categorylogic logic; File Size187KB，2 Pages; ManufacturerSUSUMU; Environmental Compliance

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BL1L5MT160ST1 Overview

Active Delay Line, 1-Func, PBGA14, SMT-14

BL1L5MT160ST1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	BGA,
Contacts	14
Reach Compliance Code	unknown
JESD-30 code	R-PBGA-B14
length	10.06 mm
Logic integrated circuit type	ACTIVE DELAY LINE
Number of functions	1
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output impedance nominal value (Z0)	50 Ω
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	250
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	3.1 mm
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	10
Total delay nominal (td)	1.6 ns
width	6.4 mm
Base Number Matches	1

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BL1L series, ball-grid-array thin

film delay lines

These delay lines offer the same excellent frequency performance as GL delay lines but

come in a solder bump configuration that takes up less board space than the GL series. As with all of TFT s delay

lines, these feature stripline conductors on ceramic for high speed, high stability performance.

SPECIFICATIONS

6.4 0.20

H

Now under development

Mechanical

7 8

1.27 typ

10.20

0.20

Time Delay

0.1 0.9n sec

1.0 1.8n sec

1.9 2.7n sec

2.8 3.5n sec

H

1.70max

2.30max

2.80max

2.90max

Code

L

M

N

O

Equivalent circuit

3

10

1 14

1 2

0.8MAX.

13 14

PART NUMBER

1.2typ

(dimension:mm)

Electrical

Type

Time Delay

Time Delay Tolerance

Characteristic Impedance

Rated Current

DC Resistance

Insulation resistance

Operating Tem. Range

Storage Tem. Range

BL1L5

0.1 3.5n sec.(0.1n sec. Step)

0.05n sec.

50 5

100mA

1.0 /n sec. Max.

100 (DC50V)

40 85 C

55 125 C

BL1L 5 N T 250 S T1

Package

(T Tape, 1 100)

Serial code

Time Delay

(250 2.50n sec)

solder bump

Height code

Impedance

Part Code,

Number of elements

GL1L/GL2L series, SOP(small outline package)

thin film differential delay lines

These delay lines offer the same excellent frequency performance as SIP delay lines but come in a gullwinged surface mount

package. The differential SMT is useful for PECL application, and contains two identical transmission lines matched for

the time delay. Featuring a stripline shielded construction, these parts offer very low EMI/RFI, and are ideal for high

frequency/tight tolerance timing and deskew applications.

SPECIFICATIONS

13.66max

GL1L

9

Mechanical

16

Equivalent circuit

6.06max

8.35max

2

10

MS250SθE

1

1.27 0.13

8

1 3

9 11

GL2L

16

H

0.56max

(dimension : mm)

Time Delay

0.1 1.0ns

1.1 5.0ns

H

2.37max

4.85max

Code

L

M

2

15

7

10

Electrical

1 3 4 5 6 8 9 11 12 13 14 16

Type

Time Delay

GL1L

0.1 5.0ns(0.1ns step)

GL2L

0.1 3.0ns(0.1ns step)

3.5 4.5ns(0.5ns step)

0.05ns(0.1 2.9ns)

0.5/+0.1ns(3.0ns)

0.1ns(3.5 4.5ns)

0 150ppm/ C

50 5

200ps/ns

100mA

25 85 C

PART NUMBER

Time Delay Tolerance

Temp. coefficient of Td

Characteristic Impedance

Rise/fall time

Rated Currrent

Operating Temperature

0.05ns

GL1L 5 M S 250 S

Circuit : S(GL1L),D(GL2L)

Time Delay : (250 2.50ns)

Lead Frame

Height code

Impedance : (5 50V)

Part Code

susumu group catalog

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