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5962F-0153401VXX

Description
TRIPLE LINE DRIVER, DFP48, DFP-48
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size119KB,14 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

5962F-0153401VXX Overview

TRIPLE LINE DRIVER, DFP48, DFP-48

5962F-0153401VXX Parametric

Parameter NameAttribute value
MakerCobham Semiconductor Solutions
Parts packaging codeDFP
package instructionQFF,
Contacts48
Reach Compliance Codeunknown
ECCN codeEAR99
Differential outputYES
Number of drives3
Input propertiesSTANDARD
Interface integrated circuit typeLINE DRIVER
Interface standardsGENERAL PURPOSE
JESD-30 codeR-XDFP-F48
length15.875 mm
Number of functions3
Number of terminals48
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialUNSPECIFIED
encapsulated codeQFF
Package shapeRECTANGULAR
Package formFLATPACK
Certification statusNot Qualified
Maximum seat height3.048 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formFLAT
Terminal pitch0.635 mm
Terminal locationDUAL
total dose300k Rad(Si) V
maximum transmission delay2.5 ns
width9.652 mm
Base Number Matches1
Standard Products
UT54LVDS217 Serializer
Data Sheet
October 27, 2010
FEATURES
15 to 75 MHz shift clock support
Low power consumption
Power-down mode <216μW (max)
Cold sparing all pins
Narrow bus reduces cable size and cost
Up to 1.575 Gbps throughput
Up to 197 Megabytes/sec bandwidth
325 mV (typ) swing LVDS devices for low EMI
PLL requires no external components
Rising edge strobe
Operational Environment; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1 Mrad(Si)
- Latchup immune (LET > 100 MeV-cm
2
/mg)
Packaging options:
- 48-lead flatpack
Standard Microcircuit Drawing 5962-01534
- QML Q and V compliant part
INTRODUCTION
The UT54LVDS217 Serializer converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel
with the data streams over a fourth LVDS link. Every cycle of
the transmit clock 21 bits of input data are sampled and
transmitted.
At a transmit clock frequency of 75MHz, 21 bits of TTL data
are transmitted at a rate of 525 Mbps per LVDS data channel.
Using a 75MHz clock, the data throughput is 1.575 Gbit/s (197
Mbytes/sec).
The UT54LVDS217 Serializer allows the use of wide, high
speed TTL interfaces while reducing overall EMI and cable size.
All pins have Cold Spare buffers. These buffers will be high
impedance when V
DD
is tied to V
SS
.
21
CMOS/TTL INPUTS
TTL PARALLEL-TO-LVDS
TTL PARALLEL -TO-LVDS
DATA (LVDS)
TRANSMIT CLOCK IN
POWER DOWN
PLL
CLOCK (LVDS)
Figure 1. UT54LVDS217 Serializer Block Diagram
1
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