NCP5106A, NCP5106B
High Voltage, High and Low
Side Driver
The NCP5106 is a high voltage gate driver IC providing two
outputs for direct drive of 2 N−channel power MOSFETs or IGBTs
arranged in a half−bridge configuration version B or any other
high−side + low−side configuration version A.
It uses the bootstrap technique to ensure a proper drive of the
high−side power switch. The driver works with 2 independent inputs.
Features
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MARKING
DIAGRAMS
1
SOIC−8
D SUFFIX
CASE 751
8
5106x
ALYW
G
1
High Voltage Range: Up to 600 V
dV/dt Immunity
±50
V/nsec
Negative Current Injection Characterized Over the Temperature Range
Gate Drive Supply Range from 10 V to 20 V
High and Low Drive Outputs
Output Source / Sink Current Capability 250 mA / 500 mA
3.3 V and 5 V Input Logic Compatible
Up to V
CC
Swing on Input Pins
Extended Allowable Negative Bridge Pin Voltage Swing to −10 V
for Signal Propagation
Matched Propagation Delays Between Both Channels
Outputs in Phase with the Inputs
Independent Logic Inputs to Accommodate All Topologies (Version A)
Cross Conduction Protection with 100 ns Internal Fixed Dead Time
(Version B)
Under V
CC
LockOut (UVLO) for Both Channels
Pin−to−Pin Compatible with Industry Standards
These are Pb−Free Devices
1
PDIP−8
P SUFFIX
CASE 626
NCP5106x
AWL
YYWWG
1
DFN10
MN SUFFIX
CASE 506DJ
NCP5106
x
A
L or WL
Y or YY
W or WW
G or
G
5106x
ALYWG
G
Typical Applications
•
Half−Bridge Power Converters
•
Any Complementary Drive Converters (Asymmetrical Half−Bridge,
Active Clamp) (A Version Only).
•
Full−Bridge Converters
= Specific Device Code
= A or B version
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT INFORMATION
VCC
IN_HI
IN_LO
GND
1
VBOOT
DRV_HI
BRIDGE
DRV_LO
8 Pin Package
VCC
IN_HI
IN_LO
GND
DRV_LO
1
VBOOT
NC
DRV_HI
NC
BRIDGE
10 Pin DFN Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 16 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2017
1
February, 2017 − Rev. 9
Publication Order Number:
NCP5106/D
NCP5106A, NCP5106B
Vbulk
+
C1
D4
Q1
C3
GND
NCP1395
Vcc
IN_HI DRV_HI
IN_LO
Bridge
Q2
C6
GND DRV_LO
GND
GND
GND
D3
GND
U2
R1
NCP5106
U1
VBOOT
C4
Lf
Out−
D2
T1
D1
L1
+
C3
Out+
GND
Vcc
Figure 1. Typical Application Resonant Converter (LLC type)
Vbulk
+
C1
D4
Q1
C3
GND
U1
Vcc
IN_LO
VBOOT
Bridge
D2
C6
Q2
GND
D3
GND
U2
R1
IN_HI DRV_HI
Out−
GND DRV_LO
C4
T1
D1
C5
L1
+
C3
Out+
GND
Vcc
MC34025
GND
GND
NCP5106
Figure 2. Typical Application Half Bridge Converter
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NCP5106A, NCP5106B
VCC
IN_HI
PULSE
TRIGGER
LEVEL
SHIFTER
S Q
R Q
UV
DETECT
DRV_HI
VCC
UV
DETECT
VBOOT
BRIDGE
VCC
GND
GND
IN_LO
DELAY
DRV_LO
GND
GND
GND
GND
GND
Figure 3. Detailed Block Diagram: Version A
VCC
IN_HI
VCC
UV
DETECT
PULSE
TRIGGER
LEVEL
SHIFTER
S Q
R Q
UV
DETECT
VBOOT
DRV_HI
BRIDGE
VCC
GND
CROSS
CONDUCTION
PREVENTION
GND
IN_LO
DELAY
DRV_LO
GND
GND
GND
Figure 4. Detailed Block Diagram: Version B
PIN DESCRIPTION
Pin Name
IN_HI
Description
Logic Input for High Side Driver Output in Phase
Logic Input for Low Side Driver Output in Phase
Ground
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IN_LO
GND
DRV_LO
V
CC
Low Side Gate Drive Output
Low Side and Main Power Supply
Bootstrap Power Supply
V
BOOT
DRV_HI
High Side Gate Drive Output
BRIDGE
NC
Bootstrap Return or High Side Floating Supply Return
Removed for creepage distance (DFN package only)
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NCP5106A, NCP5106B
MAXIMUM RATINGS
Rating
V
CC
V
CC_transient
V
BRIDGE
V
BRIDGE
V
BOOT−
V
BRIDGE
V
DRV_HI
V
DRV_LO
dV
BRIDGE
/dt
V
IN_XX
Main power supply voltage
Main transient power supply voltage:
IV
CC_max
= 5 mA during 10 ms
VHV: High Voltage BRIDGE pin
Allowable Negative Bridge Pin Voltage for IN_LO Signal Propagation to DRV_LO
(see characterization curves for detailed results)
VHV: Floating supply voltage
VHV: High side output voltage
Low side output voltage
Allowable output slew rate
Inputs IN_HI, IN_LO
ESD Capability:
− HBM model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
− Machine model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
Latch up capability per JEDEC JESD78
R
qJA
Power dissipation and Thermal characteristics
PDIP−8: Thermal Resistance, Junction−to−Air
SO−8: Thermal Resistance, Junction−to−Air
DFN10 4x4: Thermal Resistance, Junction−to−Ambient 1 Oz Cu
DFN10 4x4:
50 mm
2
Printed Circuit Copper Clad
Storage Temperature Range
Maximum Operating Junction Temperature
°C/W
100
178
162
−55 to +150
+150
°C
°C
Symbol
Value
−0.3 to 20
23
−1 to 600
−10
−0.3 to 20
V
BRIDGE
− 0.3 to
V
BOOT
+ 0.3
−0.3 to V
CC
+ 0.3
50
−1.0 to V
CC
+ 0.3
2
200
Unit
V
V
V
V
V
V
V
V/ns
V
kV
V
T
ST
T
J_max
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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NCP5106A, NCP5106B
ELECTRICAL CHARACTERISTIC
(V
CC
= V
boot
= 15 V, V
GND
= V
bridge
, −40°C < T
J
< 125°C, Outputs loaded with 1 nF)
T
J
−40°C to 125°C
Rating
OUTPUT SECTION
Output high short circuit pulsed current V
DRV
= 0 V, PW
v
10
ms
(Note 1)
Output low short circuit pulsed current V
DRV
= V
CC
, PW
v
10
ms
(Note 1)
Output resistor (Typical value @ 25°C) Source
Output resistor (Typical value @ 25°C) Sink
High level output voltage, V
BIAS
−V
DRV_XX
@ I
DRV_XX
= 20 mA
Low level output voltage V
DRV_XX
@ I
DRV_XX
= 20 mA
DYNAMIC OUTPUT SECTION
Turn−on propagation delay (Vbridge = 0 V)
Turn−off propagation delay (Vbridge = 0 V or 50 V) (Note 2)
Output voltage rise time (from 10% to 90% @ V
CC
= 15 V) with 1 nF load
Output voltage fall time (from 90% to 10% @V
CC
= 15 V) with 1 nF load
Propagation delay matching between the High side and the Low side @ 25°C (Note 3)
Internal fixed dead time (only valid for B version) (Note 4)
Minimum input width that changes the output
Maximum input width that does not change the output
INPUT SECTION
Low level input voltage threshold
Input pull−down resistor (V
IN
< 0.5 V)
High level input voltage threshold
Logic “1” input bias current @ V
IN_XX
= 5 V @ 25°C
Logic “0” input bias current @ V
IN_XX
= 0 V @ 25°C
SUPPLY SECTION
V
CC
UV Start−up voltage threshold
V
CC
UV Shut−down voltage threshold
Hysteresis on V
CC
Vboot Start−up voltage threshold reference to bridge pin
(Vboot_stup = Vboot − Vbridge)
Vboot UV Shut−down voltage threshold
Hysteresis on Vboot
Leakage current on high voltage pins to GND
(V
BOOT
= V
BRIDGE
= DRV_HI = 600 V)
Consumption in active mode (V
CC
= Vboot, fsw = 100 kHz and 1 nF load on both driv-
er outputs)
Consumption in inhibition mode (V
CC
= Vboot)
V
CC
current consumption in inhibition mode
Vboot current consumption in inhibition mode
V
CC
_stup
V
CC
_shtdwn
V
CC
_hyst
Vboot_stup
Vboot_shtdwn
Vboot_hyst
I
HV_LEAK
ICC1
ICC2
ICC3
ICC4
8.0
7.3
0.3
8.0
7.3
0.3
−
−
−
−
−
8.9
8.2
0.7
8.9
8.2
0.7
5
4
250
200
50
9.9
9.1
−
9.9
9.1
−
40
5
400
−
−
V
V
V
V
V
V
mA
mA
mA
mA
mA
V
IN
R
IN
V
IN
I
IN+
I
IN−
−
−
2.3
−
−
−
200
−
5
−
0.8
−
−
25
2.0
V
kW
V
mA
mA
SOIC−8, PDIP−8
DFN10
t
ON
t
OFF
tr
tf
Dt
DT
t
PW1
t
PW2
−
−
−
−
−
65
−
20
15
100
100
85
35
20
100
−
−
−
170
170
160
75
35
190
50
−
−
ns
ns
ns
ns
ns
ns
ns
ns
I
DRVsource
I
DRVsink
R
OH
R
OL
V
DRV_H
V
DRV_L
−
−
−
−
−
−
250
500
30
10
0.7
0.2
−
−
60
20
1.6
0.6
mA
mA
W
W
V
V
Symbol
Min
Typ
Max
Units
1. Parameter guaranteed by design.
2. Turn−off propagation delay @ Vbridge = 600 V is guaranteed by design.
3. See characterization curve for
Dt
parameters variation on the full range temperature.
4. Version B integrates a dead time in order to prevent any cross conduction between DRV_HI and DRV_LO. See timing diagram of Figure 10.
5. Timing diagram definition see: Figure 7, Figure 8 and Figure 9.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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