EEWORLDEEWORLDEEWORLD

Part Number

Search

305-012-521-568

Description
Card Edge Connector
CategoryThe connector    The connector   
File Size911KB,2 Pages
ManufacturerEDAC
Environmental Compliance
Download Datasheet Parametric View All

305-012-521-568 Online Shopping

Suppliers Part Number Price MOQ In stock  
305-012-521-568 - - View Buy Now

305-012-521-568 Overview

Card Edge Connector

305-012-521-568 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerEDAC
Reach Compliance Codecompliant
Connector typeCARD EDGE CONNECTOR
Contact to complete cooperationGOLD OVER NICKEL
Contact completed and terminatedTIN OVER NICKEL
Contact materialCOPPER ALLOY
JESD-609 codee3
Manufacturer's serial number305
Base Number Matches1
DSP program simulation problem
I just started learning DSP recently. I encountered several problems while studying a project program. Please help me. I have only learned it for a week and only know the general questions. Please for...
salutwl DSP and ARM Processors
What is the difference between an IEEE address and a 16-bit short address?
Which expert can help me explain it?...
cnsxgh RF/Wirelessly
Unable to load NK.NB0
I use the card swipe method to load NK.NB0. Why can't the NK.NB0 BOOT boot I compiled and generated recognize and load the serial port print information as follows. System ready! Preparing for downloa...
流氓法拉利 Embedded System
The latest research areas of FPGA
Dear electronics enthusiasts and experts, I would like to ask you, what is the latest research field of FPGA? In what areas can new breakthroughs be made? Thank you...
ky0611 FPGA/CPLD
LPC11C14 GPIO state cannot be changed
Below is the initialization of pin PIO2_11. The original intention was to initialize the pin to output low level, but it has always been high level....
einslssac NXP MCU
Dear experts, please help me with the xilinx and altera single port RAM simulation problem
[i=s] This post was last edited by xujiangyu0619 on 2015-1-15 23:00 [/i] When simulating Xilinx and Altera single-port RAM, it is found that Xilinx RAM uses one less clock cycle than Altera when readi...
xujiangyu0619 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1101  560  1563  2620  2685  23  12  32  53  55 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号