PCMCIA Flash Memory Card
FVF Series
FVF Value Series Flash Memory Card
General Description
The FVF Value Series Flash memory cards offer a low cost
linear Flash solid state storage solution for code and data
storage, high performance disk emulation, mobile PC and
embedded applications.
FVF series cards offer memory capacities from 4MB to
64MB, with 128kB block erase size.
The WEDC Value series is based on Intel MLC, Strata Flash
memories. Cards are based on the two families of memory
components:
FVF0x
built with: 28F640J5, 28F320J5
FVF1x
built with: 28F128J3, 28F640J3, 28F320J3
These flash devices support the Common Flash Interface
(CFI) programming algorithm, a standard that allows system
level software to evaluate the flash configuration, electrical
characteristic, programming parameters and supported
functions. CFI is intended to support future upgrades with
universal programming algorithms, so there is no longer a
need for continued programming software modification and
updates. Systems should be able to recognize and support all
devices to allow universal expansion/upgrade path.
The symmetrically blocked architecture and single supply
(5V for FVF0x and universal 3.3V or 5V for FVF1x cards)
operation provides a cost effective, high performance,
nonvolatile storage solution. The PC Card form factor offers
an industry standard pinout and mechanical outline, allowing
density upgrades without system design changes.
The Value series is designed as a simple x16 linear array of
Flash devices. One Flash device provides the lower and
upper bytes for the 16 bit access. Other modes of operation
are also supported (See Functional Truth Table on page 5)
WEDC’s standard Value Series Flash Card is shipped with
no attribute memory or CIS (Card Information Structure)
information. An option for 2KB of attribute memory with
CIS information is available. The CIS for the WEDC Value
series may also be stored in Block 0 (even bytes, D0 - D7
only) of the Flash memory. This option is available by
request only.
WEDC’s standard cards are shipped with WEDC’s Logo.
Cards are also available with blank housings (no Logo). The
blank housings are available in both a recessed (for label)
and flat housing. Please contact WEDC sales representative
for further information on Custom artwork.
October 2001 Rev. 1 - ECO #xxxxx
1
PC Card Products
4, 8, 16, 32, 48 and 64MB(Intel Strata Flash )
Features
•
PCMCIA 2.1 (PC Card 97) compatible
- Type I or Type II Form Factor
•
Low cost Linear Flash Card
•
Single Supply Operation
•
FVF0x - 5V
•
FVF1x - 5V or 3.3V (Note 1)
•
Fast Read Performance
- 200ns Maximum Access Time
•
Based on MLC Strata Flash Components
•
Common Flash Interface (CFI) compliant
•
High Performance Random Writes
- 6µs Typical per Byte Write Time, using 32Byte
Write buffer
•
Automated Write and Erase Algorithms
•
High Write/Erase Endurance:
100,000 Write/Erase Cycles
•
Low Power Consumption
•
150µA Standby Current
•
75mA Max Byte Write Current
Note 1:
FVF1x supports wide, universal operating
voltage: 3V to 5V.
That means the card will work in 3.3V systems
as well as in 5V systems. This feature may
allow easy exchange of data between multiple
and different systems and provide easy
upgrade / expansion path.
PCMCIA Flash Memory Card
FVF Series
Manufacturer and Device ID codes
Device
Manuf ID Device ID
89h
89h
89h
89h
89h
18h
17h
16h
15h
14h
FVF block diagram
Addresses
A1..A25
(note 1)
Int 28F128J3
Int 28F640J3
Int 28F320J3
Int 28F640J5
Int 28F320J5
Addresses
A1..A25
/CSn
/CE
/CE
/CE
OE#
Buffers and Control logic
WE#
/CS1
/CS0
PCMCIA interface
CE1#
CE2#
DATA Low
D15..8
D15..8
Memory
High Byte
D7..0
Memory
Low Byte
28F640J5
28F320J5
28F128J3
28F640J3
28F320J3
DATA Low
D7..0
R/B /PD
BVD1
BVD2
Vcc
Attribute Memory
(optional)
RDY/BSY#
RST
VS1
VS2
CD1
CD2
Notes:
1.
A25..23 pulled down by 100kΩ resistors
2.
Open for FVF0x;
GND for FVF1x (3.3V operation)
October 2001 Rev. 1 - ECO #xxxxx
2
PC Card Products
Reset
Circuit
- pull down resistor Typ. 100kΩ
open/GND
(note 2)
open
- pull up resistor Min. 10kΩ
PCMCIA Flash Memory Card
FVF Series
For information regarding modes of operation, commands, and programming
details for the memory components, please consult the Intel 28F128J3A,
28F640J5 data sheets.
Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing of the
status register, and, when V
PEN
= V
PENH
, block erasure, program, and lock-bit configuration.
The Block Erase command requires appropriate command data and an address within the block to be erased. The
Byte/Word Program command requires the command and address of the location to be written. Set Block Lock-Bit
commands require the command and block within the device to be locked. The Clear Block Lock-Bits command
requires the command and address within the device.
The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE# is
active. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge
of CE1# or CE2# that disables the card. Standard microprocessor write timings are used.
October 2001 Rev. 1 - ECO #xxxxx
3
PC Card Products
PCMCIA Flash Memory Card
FVF Series
Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
RDY/BSY#
Vcc
Vpp1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
WP
GND
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
Ground
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
Data bit 1
Data bit 2
Write Potect
Ground
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND
CD1#
DQ11
DQ12
DQ13
DQ14
DQ15
CE2#
VS1
RFU
RFU
A17
A18
A19
A20
A21
Vcc
Vpp2
A22
A23
A24
A25
VS2
RST
Wait#
RFU
REG#
BVD2
BVD1
DQ8
DQ9
DQ10
CD2#
GND
Ground
O
Card Detect 1
LOW
I/O
Data bit 11
I/O
Data bit 12
I/O
Data bit 13
I/O
Data bit 14
I
Data bit 15
I
Card Enable 2
LOW
O Voltage Sense 1 N.C.or GND (2)
Reserved
Reserved
I
Address bit 17
I
Address bit 18
I
Address bit 19
I
Address bit 20
I
Address bit 21
Supply Voltage
Prog. Voltage
N.C.
I
Address bit 22
I
Address bit 23
I
Address bit 24
I
Address bit 25
O Voltage Sense 2
N.C.
I
Card Reset
HIGH
LOW
O Extended Bus cycle
Reserved
I Attrib Mem Select N.C (optional)
O Bat. Volt. Detect 2
O Bat. Volt. Detect 1
I/O
Data bit 8
I/O
Data bit 9
O
Data bit 10
O
Card Detect 2
LOW
Ground
LOW
LOW
LOW
LOW (1)
N.C.
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
HIGH
Notes:
1. RDY/BSY signal is an open drain output, with MIN 47kΩ pull-up resistor.
2. N.C. for FVF0x (5V only operation)
GND for FVF1x (3.3V or 5V operation)
Mechanical
1.0mm ± 0.05
(0.039”)
Interconnect area
1.6mm ± 0.05
(0.063”)
10.0mm MIN
(0.400”)
3.0mm MIN
Substrate area
54.0mm ± 0.10
(2.126”)
1.0mm ± 0.05
(0.039”)
85.6mm ± 0.20
(3.370”)
10.0mm MIN
(0.400”)
3.3mm ± T1 (0.130”)
T1=0.10mm interconnect area
T1=0.20mm substrate area
October 2001 Rev. 1 - ECO #xxxxx
4
PC Card Products
PCMCIA Flash Memory Card
FVF Series
Card Signal Description
Symbol
A0 - A25
Type
INPUT
Name and Function
ADDRESS INPUTS:
A0 through A25 enable direct addressing of up to 64MB of
memory on the card. Signal A0 is used only in 8 bit configuration (CE1# active
CE2# not active). A0 is disregarded in 16 bit operation (CE1# and CE2# active).
The system should not try to access memory beyond the card density because the
card will return undefined data. (The upper addresses are decoded).
DATA INPUT/OUTPUT:
DQ0 THROUGH DQ15 constitute the bi-directional
databus. DQ0 - DQ7 constitute the lower (even) byte and DQ8 - DQ15 the upper
(odd) byte. DQ15 is the MSB.
CARD ENABLE 1 AND 2:
CE1# enables even byte accesses, CE2# enables odd
byte accesses. (See below the Functional Truth Table).
OUTPUT ENABLE:
Active low signal enabling read data from the memory card.
WRITE ENABLE:
Active low signal gating write data to the memory card.
READY/BUSY OUTPUT:
Indicates status of internally timed erase or program
algorithms. A high output indicates that the card is ready to accept accesses.
CARD DETECT 1 and 2:
Provide card insertion detection. These signals are
connected to ground internally on the memory card. The host socket interface
circuitry shall supply 10K-ohm or larger pull-up resistors on these signal pins.
WRITE PROTECT:
This signal is pulled low internally. This signifies write
protect = "off " for all cases.
PROGRAM/ERASE POWER SUPPLY:
Not connected for 5V only card.
CARD POWER SUPPLY:
(5.0V for FVF0x or 3V to 5V for FVF1x)
GROUND:
ATTRIBUTE MEMORY SELECT:
connected only on cards built with optional
attribute memory. (see Note 1)
RESET:
Active high signal for placing card in Power-on default state.
WAIT:
This signal is pulled high internally for compatibility. No wait states are
generated.
BATTERY VOLTAGE DETECT:
These signals are pulled high to maintain
SRAM card compatibility.
VOLTAGE SENSE:
Notifies the host socket of the card's VCC requirements. VS1
and VS2 are open to indicate a 5V; VS1=GND and VS2 open indicate possibility
to work in 3.3V systems.
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD:
pin may be driven or left floating
DQ0 - DQ15
INPUT /
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
CE1#, CE2#
OE#
WE#
RDY/BSY#
CD1#, CD2#
WP
VPP1, VPP2
VCC
GND
REG#
RST
WAIT#
BVD1, BVD2
VS1, VS2
OUTPUT
N.C.
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
RFU
N.C.
Functional Truth Table
READ function
Common Memory
Attribute Memory (optional)
Function Mode
Standby Mode
Byte Access (8 bits)
(3)
Word Access (16 bits)
(3)
Odd-Byte Only Access
WRITE function
CE2# CE1#
H
H
H
L
H
L
L
L
L
H
H
H
H
L
L
H
L
L
L
H
A0
X
L
H
X
X
X
L
H
X
X
OE#
X
L
L
L
L
X
H
H
H
H
WE#
X
H
H
H
H
X
L
L
L
L
REG# D15-D8
D7-D0
X
High-Z
High-Z
H
(1)
High-Z Even-Byte
H
(1)
High-Z
Odd-Byte
H
(1)
Odd-Byte Even-Byte
H
(1)
Odd-Byte
High-Z
X
X
X
H
(1)
X
Even-Byte
H
(1)
X
Odd-Byte
H
(1)
Odd-Byte Even-Byte
H
(1)
Odd-Byte
X
REG# D15-D8
D7-D0
X
High-Z
High-Z
L
High-Z Even-Byte
L
High-Z Not Valid
L Not Valid Even-Byte
L Not Valid
High-Z
X
L
L
L
L
X
X
X
X
X
X
Even-Byte
X
Even-Byte
X
Standby Mode
Byte Access (8 bits)
(3)
Word Access (16 bits)
(3)
Odd-Byte Only Access (2)
Notes:
1. For standard cards without Attribute memory this signal is not connected:
X – don’t care
2. Operation in Shaded row not supported: Accessing memory in this mode may alter data in lower byte
For proper operation signals CE1# and CE2# should be connected together (for 16 bit operation) or signal
CE2# should be always in High state (for 8bit operation)
3. Switching between byte access mode (8 bit) and word access mode (16 bit) requires a 1ms setup time.
October 2001 Rev. 1 - ECO #xxxxx
5
PC Card Products
京公网安备 11010802033920号
EEWORLD
