P
R E L I M I N A R Y
D
A TA
S
H E E T
Si554
Q
U A D
F
R E Q U E N C Y
VCXO (10 MH
Z
Features
Available with any-rate output
frequencies from 10–945 MHz and
select frequencies to 1.4 GHz
Four selectable output frequencies
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
TO
1.4 GH
Z
)
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL, LVDS
& CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Applications
SONET/SDH
xDSL
10 GbE LAN / WAN
Low jitter clock generation
Optical Modules
Clock and data recovery
Ordering Information:
See page 8.
Description
The Si554 quad frequency VCXO utilizes Silicon Laboratories advanced
DSPLL
®
circuitry to provide a very low jitter clock for all output frequencies.
The Si554 is available with any-rate output frequency from 10 to 945 MHz
and select frequencies to 1400 MHz. Unlike traditional VCXOs where a
different crystal is required for each output frequency, the Si554 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si554 IC-based VCXO is factory configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
Pin Assignments:
See page 7.
(Top View)
FS[1]
7
V
C
1
2
3
8
FS[0]
6
5
4
V
DD
OE
GND
CLK–
CLK+
Functional Block Diagram
V
DD
CLK- CLK+
FS1
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL
®
Clock Synthesis
FS0
ADC
V
c
OE
GND
Preliminary Rev. 0.3 5/06
Copyright © 2006 by Silicon Laboratories
Si554
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si554
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
1
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Supply Current
I
DD
Output enabled
TriState mode
Output Enable (OE)
2
V
IH
V
IL
Operating Temperature Range
T
A
Min
2.97
2.25
1.71
—
—
0.75 x V
DD
—
–40
Typ
3.3
2.5
1.8
90
60
—
—
—
Max
3.63
2.75
1.89
—
—
—
0.5
85
mA
V
Units
V
ºC
Notes:
1.
Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 8 for further details.
2.
OE pin includes a 17 kΩ pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
Table 2. V
C
Control Voltage Input
Parameter
Control Voltage Tuning Slope
1,2,3
Symbol
K
V
Test Condition
10 to 90% of V
DD
Min
—
Typ
45
90
135
180
±1
±5
10.0
—
3/8 x V
DD
Max
—
Units
ppm/V
Control Voltage Linearity
4
L
VC
BSL
Incremental
–5
–10
9.3
500
+5
+10
10.7
—
—
V
DD
%
kHz
kΩ
V
V
Modulation Bandwidth
V
C
Input Impedance
Nominal Control Voltage
Control Voltage Tuning Range
BW
Z
VC
V
CNOM
V
C
@ f
O
—
0
Notes:
1.
Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 8.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3.
K
V
variation is ±28% of typical values.
4.
BSL determined from deviation from best straight line fit with V
C
ranging from 10 to 90% of V
DD
. Incremental slope
determined with V
C
ranging from 10 to 90% of V
DD
.
2
Preliminary Rev. 0.3
Si554
Table 3. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency
1,2,3
Temperature Stability
1,4
Symbol
f
O
∆f/f
O
Test Condition
LVDS/CML/LVPECL
CMOS
T
A
= –40 to +85 ºC
Min
10
10
–20
–50
–100
±25
Frequency drift over 15
year life.
t
OSC
Typ
—
—
—
—
—
—
—
—
—
Max
945
160
+20
+50
+100
±150
±10
10
20
Units
MHz
ppm
ppm
ppm
ms
ms
Absolute Pull Range
1,4
Aging
Power up Time
5
Settling Time After FS[1:0] Change
APR
—
—
t
FRQ
Both FS[1] and FS[0]
changing simultaneously
—
Notes:
1.
See Section 3. "Ordering Information" on page 8 for further details.
2.
Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3.
Nominal output frequency set by V
CNOM
= 3/8 x V
DD
.
4.
Selectable parameter specified by part number.
5.
Time from power up or tristate mode to f
O
(to within ±1 ppm of f
O
).
Table 4. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
Symbol
V
O
V
OD
V
SE
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
swing (diff)
Min
V
DD
– 1.42
1.1
0.5
1.125
0.32
Typ
—
Max
V
DD
– 1.25
1.9
0.93
1.275
0.50
Units
V
V
PP
V
PP
V
V
PP
—
—
1.20
0.40
LVDS Output Option
2
V
O
V
OD
CML Output Option
2
CMOS Output Option
3
Rise/Fall time (20/80%)
Symmetry (duty cycle)
V
O
V
OD
V
OH
V
OL
t
R,
t
F
mid-level
swing
(diff)
I
OH
= 32 mA
I
OL
= 32 mA
—
0.70
0.8 x V
DD
V
DD
– 0.75
0.95
—
—
—
1
—
—
1.20
V
DD
V
V
PP
V
—
—
—
45
0.4
350
—
55
LVPECL/LVDS/CML
CMOS with CL = 15 pF
LVPECL:
LVDS:
CMOS:
V
DD
– 1.3 V (diff)
1.25 V (diff)
V
DD
/2
ps
ns
%
SYM
Notes:
1.
50
Ω
to V
DD
– 2.0 V.
2.
R
term
= 100
Ω
(differential).
3.
C
L
= 15 pF
Preliminary Rev. 0.3
3
Si554
Table 5. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)
1,2,3
for F
OUT
> 500 MHz
Symbol
Test Condition
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Phase Jitter (RMS)
1,2,3
for F
OUT
of 125 to 500 MHz
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
0.35
0.38
0.43
0.41
0.52
0.46
0.64
0.52
0.42
0.58
0.48
0.60
0.57
0.64
0.67
0.68
Max
—
—
—
—
—
—
—
—
ps
—
—
—
—
—
—
—
—
Units
ps
φ
J
φ
J
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Notes:
1.
Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3.
See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
Table 6. CLK± Output Period Jitter
Parameter
Period Jitter*
for F
OUT
< 160 MHz
Symbol
J
PER
Test Condition
RMS
Peak-to-Peak
Min
—
—
Typ
2
14
Max
—
—
Units
ps
*Note:
Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.
4
Preliminary Rev. 0.3
Si554
Table 7. CLK± Output Phase Noise (Typical)
Configuration
f
C
K
V
Output
Offest Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
–94
–117
–128
–135
–138
–143
n/a
74.25 MHz
45 ppm/V
CMOS
L
(f)
–74
–98
–112
–122
–134
–144
–147
–77
–101
–114
–118
–128
–144
–147
300 MHz
90 ppm/V
LVPECL
622.08 MHz
45 ppm/V
LVPECL
Units
dBc/Hz
Preliminary Rev. 0.3
5
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