NCV8855
Quad-Output Automotive
System Power Supply IC
with Integrated High-Side
2A Switch
The NCV8855 is a multiple output controller / regulator IC with an
integrated high−side load switch. The NCV8855 addresses automotive
radio system and instrument cluster power supply requirements. In
addition to the high−side load switch, the NCV8855 includes a
switch−mode power supply (SMPS) buck controller, a 2.5 A SMPS
buck regulator and two low dropout (LDO) linear regulator
controllers. The NCV8855 in combination with the ultra−low
quiescent current NCV861x IC forms an eight−output automotive
radio or instrument cluster power solution. The NCV8855 has an
internally set switching frequency of 170 kHz, with a SYNC pin for
external frequency synchronization.
The NCV8855 is intended to supply power to various loads, such as
a tuner, CD logic, audio processor and CD / tape control within a car
radio. The high−side switch can be used for a CD / tape mechanism or
switching an electrically−powered antenna or display unit. In an
instrument cluster application, the NCV8855 can be used to power
graphics display, flash memory and CAN transceivers. In addition, the
high−side switch can be used to limit power to a TFT display during a
battery over−voltage condition.
Features
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MARKING
DIAGRAM
1
1 40
40 PIN QFN, 6x6
MN SUFFIX
CASE 488AR
A
WL
YY
WW
G
NCV8855
AWLYYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
†
2500 / Tape &
Reel
•
•
•
•
•
•
•
•
•
•
•
•
•
•
< 1
mA
Shutdown Current
Meets ES−XW7T−1A278−AB Test Pulse G – Loaded Conditions
V
IN
Operating Range 9.0 to 18.0 V
1 SMPS Controller with Adjustable Current Limit
1 SMPS Regulator with Internal 300 mW NMOS Switch
2 LDO Controllers with Current Limit and Short Circuit Protection
1 High−side Load Switch with Internal 300 mW NMOS FET
Adjustable Output Voltage for All Controllers / Regulators
800 mV,
$1%
Reference Voltage
System Enable Pin
Single Enable Pin for Both LDO Controllers
Independent Enable for High−side Load Switch
Thermal Shutdown with Thermal Warning Indicator
This is a Pb−Free Device
NCV8855BMNR2G QFN−40
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
•
Automotive Radio
•
Instrument Cluster, Driver Information System (DIS)
©
Semiconductor Components Industries, LLC, 2010
May, 2010
−
Rev. 1
1
Publication Order Number:
NCV8855/D
NCV8855
TYPICAL APPLICATION SCHEMATIC SHOWING DETAILED BLOCK DIAGRAM
DRV_VPP
SYS _EN
22
5
VIN
Bandgap
V1
VR
DRV_VPP
I
LIMIT
VIN
5V_IC
I
LIMIT
35
5V_IC
V1
VR
VIN
LDO
36
11
DRAIL
BST2
VIN_SW
VBATT
VBATT
BST1
Q1
GH1
SN1
Q2
GL1
25
Gate Control
24
23
21
QS
QR
CLK1
CLK2
S Q
R
I
LIMIT
V
REF
10
VOUT1
9
SS2
SN2
D1
VOUT2
OCSET
ILIMIT
27
SS1
V
REF
EA
RAMP1
70%
V
REF
SCP
SCP
RAMP2
EA
3
2
SW_FB2
COMP2
SYNC
SW_FB1
COMP1
29
30
DRV_VPP
5V_IC
UVLO
CLK1
RAMP1
CLK2
RAMP2
OSC
180
°
out−of−phase
4
HOT_FLG
8
TWARN1
TWARN2
Main Logic / Fault
Control
TSD1
TSD2
Int. rails
and
references
V REF
5V_IC
I
LIMIT
7
6
HS_EN
LDO_EN
VOUT1
ISNS1+
ISNS1−
40
39
1
38
I
LIMIT
31
32
ISNS2+
ISNS2−
LR _G2
LR_FB2
Q4
VBATT
VOUT3
Q3
LR_G1
LR_FB1
V
REF
EA
EA
33
34
VOUT4
SCP
70% V
REF
VBATT
VIN
26
VIN
SCP
70% V
REF
Control
CLK1
HS_OUT
HS_S
28
Current
Limit
Vneg
clamp
Vhigh
clamp
Charge
Pump
37
AGND
20
PGND
Figure 1. Application Schematic / Block Diagram
Components
D1
Q1, Q2
Q3, Q4
Part Number
MBRS4201T3
NTD24N06
NTD20P06LT4G
Value
200 V, 4 A, Schottky, 0.61 V Vf, SMC
60 V, N type MOSFET, 32 mW , DPAK
−60V,
P type MOSFET, 130 mW, DPAK
Manufacturer
ON Semiconductor
ON Semiconductor
ON Semiconductor
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2
NCV8855
PIN FUNCTION DESCRIPTIONS
Pin No.
5
6
7
8
22
35
36
4
37
Symbol
SYS_EN
LDO_EN
HS_EN
HOT_FLG
DRV_VPP
5V_IC
DRAIL
SYNC
AGND
Description
Main enable pin for the IC. A logic high on this pin will enable the part. Leaving this pin floating or driving it to
ground will place the IC in shutdown mode.
Enable pin for both LDO controllers. A logic high on this pin will enable both LDO controllers. If this pin is left
floating, an internal pull down keeps the LDOs disabled.
Enable pin for the high−side load switch. A logic high on this pin will enable the HSS. If this pin is left floating,
an internal pull down keeps the HSS disabled.
Thermal warning indicator. This pin provides an early warning signal of an impending thermal shutdown.
Output of the internal 7.2 V linear regulator. Bypass this pin with 1
mF
to ground.
Output of the internal 5 V linear regulator. Bypass this pin with 0.1
mF
to ground.
Output of the internal 4.2 V linear regulator. Bypass this pin with 0.1
mF
to ground.
Synchronization pin. Use this pin to synchronize the internal oscillator to an external clock. If synchronization
is not used, connect this pin to AGND.
Analog ground. Reference point for internal signals.
SWITCH−MODE POWER SUPPLY 1 (SMPS1) PIN CONNECTIONS
27
29
30
OCSET
SW_FB1
COMP1
Overcurrent set pin, used to set the current limit threshold. A resistor connected from this pin and the upper
MOSFET Drain sets the current limit protection level.
Output voltage feedback pin. Connect a resistor divider network to VOUT1 to set the desired output voltage.
This pin is the output of the error amplifier and the non-inverting input of the PWM comparator. Use
this pin in conjunction with the SW_FB1 pin to compensate the voltage-mode control feedback
loop.
This pin is the supply rail for the upper N−Channel MOSFET. An internal bootstrap diode brings DRV_VPP to
this pin. Connect a ceramic capacitor (C
BST1
) between this pin and the SN1 pin. A typical value for C
BST1
is
0.1
mF.
GH1 is the output pin of the internal upper N−Channel MOSFET gate driver. Keep the trace from this pin to
the gate of the upper MOSFET as short as possible to achieve the best turn−on and turn−off performance
and to reduce electro−magnetic emissions.
This pin is the return path of the upper floating gate driver. Connect this pin to the source of the upper
MOSFET. This pin is also used to sense the current flowing through the upper MOSFETs.
GL1 is the output pin of the synchronous rectifier gate driver. Connect this pin to the lower N−channel
MOSFET.
This pin is the return path for SMPS1 lower MOSFET driver current. Connect this pin to the source of the
lower MOSFET.
25
BST1
24
GH1
23
21
20
SN1
GL1
PGND
PINS NOT INTERNALLY CONNECTED TO SILICON
EP
12 thru
19
−
Exposed pad of QFN package. Connect to printed circuit board ground to improve thermal performance.
These pins can be left floating or tied to ground to improve thermal performance.
SWITCH−MODE POWER SUPPLY 2 (SMPS2) PIN CONNECTIONS
10
VIN_SW
This pin is the supply rail for the internal upper N−Channel MOSFET. Bypass this pin with a local ceramic
capacitor. Additional bulk capacitance may be required based off output requirements. Refer to application
section for more information.
Output voltage feedback pin. Connect a resistor divider network to VOUT2 to set the desired output voltage.
This pin is the output of the error amplifier and the non−inverting input of the PWM comparator. Use this pin
in conjunction with the SW_FB2 pin to compensate the voltage−controlled feedback loop.
This pin is the supply rail for the internal upper N−Channel MOSFET. An internal bootstrap diode brings
DRV_VPP to this pin. Connect a ceramic capacitor (C
BST2
) between this pin and the SN2 pin. A typical value
for C
BST2
is 0.1
mF.
Source output of the internal upper N−channel MOSFET.
3
2
11
SW_FB2
COMP2
BST2
9
SN2
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NCV8855
PIN FUNCTION DESCRIPTIONS
Pin No.
Symbol
Description
LOW DROPOUT LINEAR REGULATOR CONTROLLER 1 (LDO1) PIN CONNECTIONS
38
1
40
LR_FB1
LR_G1
ISNS1+
LDO controller output voltage feedback pin. Connect a resistor divider network to VOUT3 to set the desired
output voltage.
Error amplifier output of the LDO controller. Connect to gate of P−Channel MOSFET pass element.
Current sense positive input. Connect this pin to the supply side of the current sense resistor. This pin also
serves as the supply rail for the linear regulator controller. A local bypass capacitor with a value of 0.1
mF
to 1
mF
is recommended.
Current sense negative input. When using a current sense resistor, connect this pin to the pass element side
of the current sense resistor. If current limit is not used, connect this pin to the supply rail of the pass element.
39
ISNS1−
LOW DROPOUT LINEAR REGULATOR CONTROLLER 2 (LDO2) PIN CONNECTIONS
34
33
31
LR_FB2
LR_G2
ISNS2+
LDO controller output voltage feedback pin. Connect a resistor divider network to VOUT3 to set the desired
output voltage.
Error amplifier output of the LDO controller. Connect to gate of P−Channel MOSFET pass element.
Current sense positive input. Connect this pin to the supply side of the current sense resistor. This pin also
serves as the supply rail for the linear regulator controller. A local bypass capacitor with a value of 0.1
mF
to 1
mF
is recommended.
Current sense negative input. When using a current sense resistor, connect this pin to the pass element side
of the current sense resistor. If current limit is not used, connect this pin to the supply rail of the pass element.
32
ISNS2−
HIGH−SIDE LOAD SWITCH (HSS) PIN CONNECTIONS
26
28
VIN
HS_S
This pin is the supply rail for the internal high−side load switch, DRV_VPP and 5V_IC. Bypass this pin with a
1
mF
ceramic capacitor.
Source node output of the internal high−side N−Channel MOSFET load switch.
MAXIMUM RATINGS
(Voltages are with respect to AGND unless noted otherwise)
Pin Name
Max dc voltage (GH1, BST1, SN1, SN2, BST2, HS_S)
Negative Transient (t < 50 ns) (SN1, SN2)
Max dc voltage: 5V_IC
Max dc voltage: DRV_VPP
Max dc voltage (BST1 & GH1w/respect to SN1, GL1, BST2 w/respect to SN2)
Max dc voltage (OCSET, ISNS1+, ISNS1−, LR_G1, VIN, VIN_SW, ISNS2+, ISNS2−, LR_G2)
Peak Transient (ES−XW7T−1A278−AB Test Pulse G – Loaded Conditions)
(OCSET, ISNS1+, ISNS1−, LR_G1, VIN, VIN_SW, ISNS2+, ISNS2−, LR_G2)
Max dc voltage (SW_FB1, COMP1, LR_FB1, LDO_EN, HOT_FLG, SW_FB2, COMP2, LR_FB2, HS_EN,
SYS_EN, SYNC)
Max dc voltage: PGND
Maximum Operating Junction Temperature Range, T
J
Maximum Storage Temperature Range, T
STG
Peak Reflow Soldering Temperature: Pb−Free
60 to 150 seconds at 217°C
Value
−0.3
to 30
−2
6
9
−0.3
to 15
−0.3
to 40
−0.3
to 45
−0.3
to 7
−0.3
to 0.3
−40
to 150
−55
to +150
260 peak
Unit
V
V
V
V
V
V
V
V
V
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NCV8855
ATTRIBUTES
Description
Thermal Characteristic
R
qJA
generated from 1 sq in / 1 oz copper 1 sided PCB
ESD Capability
Human Body Model (SN1, SN2)
Human Body Model (All Others)
Machine Model
Moisture Sensitivity Level
MSL
Symbol
R
qJA
R
qJC
Value
36
3
1
2
150
1
Unit
°C/W
°C/W
kV
kV
V
RECOMMENDED OPERATING CONDITIONS
Description
VBATT range (refer to Figure 1)
Ambient Temperature range
ISNS1+
1
ISNS2+
LR_FB1
LR_FB2
Value
9 V to 18 V
−40°C
to 105°C
ISNS2−
ISNS1−
LR_G2
DRAIL
AGND
5V_IC
LR_G1
COMP2
SW_FB2
SYNC/ROSC
SYS_EN
COMP1
SW_FB1
HS_S
OCSET
VIN
Top View
BST1
GH1
SN1
DRV_VPP
GL1
LDO_EN
HS_EN
HOT_FLG
SN2
VIN_SW
HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range
−40°C
v
T
J
v
150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ELECTRICAL CHARACTERISTICS
(V
IN_SW
= V
IN
= V
ISNS1+
= V
ISNS1−
= V
ISNS2+
= V
ISNS2−
= 13.2 V, SYS_EN = LDO_EN =
SUPPLY VOLTAGES AND SYSTEM SPECIFICATION
Supply Current and Operating Voltage Range
VIN_SW quiescent current
VIN_SW shutdown current
High VIN detect voltage
High VIN detect hysteresis
VIN quiescent current
VIN shutdown current
V
OVP
No Switching, V
SW_FB2
= 1V, SN2 =
PGND1, T
J
= 25°C
SYS_EN = 0 V, T
J
= 25°C
VIN rising
VIN falling
T
J
= 25°C
SYS_EN = 0 V, T
J
= 25°C
18
0.2
175
100
18.5
0.6
4
100
500
500
19
1
mA
nA
mA
nA
V
1. Guaranteed by design, not fully tested in production.
2. Indirectly guaranteed by test coverage of other parameters.
BST2
PGND
Figure 2.
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