NCP1230
Low-Standby Power High
Performance PWM
Controller
The NCP1230 represents a major leap towards achieving low
standby power in medium−to−high power Switched−Mode Power
Supplies such as notebook adapters, off−line battery chargers and
consumer electronics equipment. Housed in a compact 8−pin package
(SOIC−8, SOIC−7, or PDIP−7), the NCP1230 contains all needed
control functionality to build a rugged and efficient power supply. The
NCP1230 is a current mode controller with internal ramp
compensation. Among the unique features offered by the NCP1230 is
an event management scheme that can disable the front−end PFC
circuit during standby, thus reducing the no load power consumption.
The NCP1230 itself goes into cycle skipping at light loads while
limiting peak current (to 25% of nominal peak) so that no acoustic
noise is generated. The NCP1230 has a high−voltage startup circuit
that eliminates external components and reduces power consumption.
The NCP1230 also features an internal latching function that can be
used for OVP protection. This latch is triggered by pulling the CS pin
above 3.0 V and can only be reset by pulling V
CC
to ground. True
overload protection, internal 2.5 ms soft−start, internal leading edge
blanking, internal frequency dithering for low EMI are some of the
other important features offered by the NCP1230.
Features
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MARKING
DIAGRAM
8
8
1
SOIC−8 VHVIC
D SUFFIX
CASE 751
1
230Dy
ALYWy
G
8
1
SOIC−7
D1 SUFFIX
CASE 751U
8
30D16
ALYWG
G
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Current−Mode Operation with Internal Ramp Compensation
Internal High−Voltage Startup Current Source for Loss−Less Startup
Extremely Low No−Load Standby Power
Skip−Cycle Capability at Low Peak Currents
Direct Connection to PFC Controller for Improved No−Load Standby
Power
Internal 2.5 ms Soft−Start
Internal Leading Edge Blanking
Latched Primary Overcurrent and Overvoltage Protection
Short−Circuit Protection Independent of Auxiliary Level
Internal Frequency Jittering for Improved EMI Signature
+500 mA/−800 mA Peak Current Drive Capability
Available in Three Frequency Options: 65 kHz, 100 kHz, and 133 kHz
Direct Optocoupler Connection
SPICE Models Available for TRANsient and AC Analysis
This is a Pb−Free Device
8
1
PDIP−7 VHVIC
P SUFFIX
CASE 626B
1
1230Pxxx
AWL
YYWWG
xxx
= Device Code: 65, 100, 133
y
= Device Code: 6, 1, 1
y
= Device Code:
5, 0, 3
A
= Assembly Location
L
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
PFC Vcc
FB
CS
GND
1
8
HV
V
CC
DRV
Typical Applications
•
High Power AC−DC Adapters for Notebooks, etc.
•
Offline Battery Chargers
•
Set−Top Boxes Power Supplies, TV, Monitors, etc.
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
May, 2015
−
Rev. 12
1
Publication Order Number:
NCP1230/D
NCP1230
HV
+
PFC_V
CC
OVP
V
out
1
2
+
CBulk
3
4
8
7
6
5
1
2
3
4
NCP1230
8
7
6
5
OVP
GN-
D
MC33262/33260
Ramp Comp
Rsense
10 k
V
CC
Cap
GND
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin No.
1
Pin Name
PFC V
CC
Function
This pin provides
the bias voltage to
the PFC controller.
Feedback Signal
Current Sense
Pin Description
This pin is a direct connection to the V
CC
pin (Pin 6) via a low impedance switch. In
standby and during the startup sequence, the switch is open and the PFC V
CC
is
shut down. As soon as the aux. winding is stabilized, Pin 1 connects to the V
CC
pin
and provides bias to the PFC controller. It goes down in standby and fault conditions.
An optocoupler collector pulls this pin low to regulate. When the current setpoint
reaches 25% of the maximum peak, the controller skips cycles.
This pin incorporates three different functions: the current sense function, an internal
ramp compensation signal and a 3.0 V latch−off level which latches the output off
until V
CC
is recycled.
−
With a drive capability of +500 mA /
−800
mA, the NCP1230 can drive large Qg
MOSFETs.
The controller accepts voltages up to 18 V and features a UVLO turn−off threshold of
7.7 V typical.
−
This pin connects to the bulk voltage and offers a lossless startup sequence. The
charging current is high enough to support the bias needs of a PWM controller
through Pin 1.
2
3
FB
CS/OVP
4
5
6
7
8
GND
DRV
V
CC
NC
HV
IC Ground
Driver Output
V
CC
Input
−
High−Voltage
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2
SW1
HV
8
1
PFC_Vcc
3.2 mAdc
/2
+
−
4Vcomp
+
Skip
0.75 Vdc
Vccreset
−
Thermal
Shutdown
4.0 Vdc
Vcc Mgmt
Vccoff=12.6V
Vccmin=7.7V
Vcclatch=5.6V
PFC_Vcc
−
PFC_Vcc
1.25 Vdc
Fault
+
VCC
Internal
Bias
20V
125 msec
Timer
6
Vdd_fb
Vdd
Error
R
S
PWM
−
+
+
−
Frequency
Modulation
Soft−Start Ramp (1V max)
2.5 msec
SS Timer
OSC
2.3 Vpp
Ramp
Latch−Off
+
−
3.0 Vdc
R
S
Q
Q
DRV
5
20k
NCP1230
Figure 2. Internal Circuit Architecture
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3
2
FB
55k
10 V
25k
18k
3
CS
LEB
10 V
4
GND
NCP1230
MAXIMUM RATINGS
(Notes 1 and 2)
Rating
Maximum Voltage on Pin 8
Maximum Current
Power Supply Voltage, Pin 6
Current
Drive Output Voltage, Pin 5
Drive Current
Voltage Current Sense Pin, Pin 3
Current
Voltage Feedback, Pin 2
Current
Voltage, Pin 1
Maximum Continuous Current Flowing from Pin 1
Thermal Resistance, Junction−to−Air, PDIP Version
Thermal Resistance, Junction−to−Air, SOIC Version
Maximum Power Dissipation @ T
A
= 25°C
Maximum Junction Temperature
Storage Temperature Range
PDIP
SOIC
Symbol
V
DS
I
C2
V
CC
I
CC2
V
DV
I
o
V
cs
I
cs
V
fb
I
fb
V
PFC
I
PFC
R
qJA
R
qJA
P
max
T
J
T
stg
Value
−0.3
to 500
100
−0.3
to 18
100
18
1.0
10
100
10
100
18
35
100
178
1.25
0.702
150
−60
to +150
Unit
V
mA
V
mA
V
A
V
mA
V
mA
V
mA
°C/W
°C/W
W
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1−6: Human Body Model 2000 V per JEDEC Standard JES22, Method A114E.
Machine Model Method 200 V per JEDEC Standard JESD22, Method A115A.
Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V.
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
ORDERING INFORMATION
Device
NCP1230D165R2G
NCP1230D65R2G
NCP1230D100R2G
NCP1230D133R2G
NCP1230P65G
NCP1230P100G
NCP1230P133G
Package
SOIC−7
(Pb−Free)
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
PDIP−7
(Pb−Free)
PDIP−7
(Pb−Free)
PDIP−7
(Pb−Free)
Shipping
†
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
50 Units/ Rail
50 Units/ Rail
50 Units/ Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NCP1230
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max values T
J
=
−40°C
to +125°C, Max T
J
= 150°C,
V
CC
= 13 V, V
PIN8
= 30 V unless otherwise noted.)
Characteristic
Supply Section
(All frequency versions, otherwise noted)
Turn−On Threshold Level, V
CC
Going Up (V
fb
= 2.0 V)
Minimum Operating Voltage after Turn−On
V
CC
Decreasing Level at which the Latch−Off Phase Ends (V
fb
= 3.5 V)
V
CC
Level at which the Internal Logic gets Reset
Internal IC Consumption, No Output Load on Pin 6 (V
fb
= 2.5 V)
Internal IC Consumption, 1.0 nF Output Load on Pin 6, F
SW
= 65 kHz
(V
fb
= 2.5 V)
Internal IC Consumption, 1.0 nF Output Load on Pin 6, F
SW
= 100 kHz
Internal IC Consumption, 1.0 nF Output Load on Pin 6, F
SW
= 133 kHz
Internal IC Consumption, Latch−Off Phase
Internal Startup Current Source
High−Voltage Current Source, 1.0 nF Load
(V
CCOFF
−0.2
V, V
fb
= 2.5 V, V
PIN8
= 30 V)
High−Voltage Current Source (V
CC
= 0 V)
Minimum Startup Voltage (I
c
= 0.5 mA, V
CCOFF
−0.2
V, V
fb
= 2.5 V)
Startup Leakage (V
PIN8
= 500 V)
Drive Output
Output Voltage Rise−Time @ C
L
= 1.0 nF, 10−90% of Output Signal
Output Voltage Fall−Time @ C
L
= 1.0 nF, 10−90% of Output Signal
Source Resistance, R
Load
300
W
(V
fb
= 2.5 V)
Sink Resistance, at 1.0 V on Pin 5 (V
fb
= 3.5 V)
Pin 1 Output Impedance (or R
dson
between Pin 1 and Pin 6 when SW1
is closed) R
load
on Pin 1 = 680
W
Current Comparator and Thermal Shutdown
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Setpoint
Tj = 25°C
Tj =
−40°C
to +125°C
I
IB
I
Limit
V
skip
V
stby−out
T
DEL CS
T
LEB
SS
T
SD
T
SD
hyste
3
3
3
−
3
3
−
−
−
−
1.010
0.979
600
1.0
−
100
−
150
−
0.02
1.063
−
750
1.25
90
200
2.5
165
25
−
1.116
1.127
900
1.5
180
350
−
−
−
mA
V
mV
V
ns
ns
ms
°C
°C
T
r
T
f
R
OH
R
OL
RPFC
5
5
5
5
1
−
−
6.0
3.0
6.0
40
15
12.3
7.5
11.7
−
−
25
18
23
ns
ns
W
W
W
I
C1
I
C2
V
HVmin
I
HVLeak
8
8
8
8
1.8
1.8
−
10
3.2
4.4
20
30
4.2
5.6
23
80
mA
mA
V
mA
V
CCOFF
V
CC(min)
V
CClatch
V
CCreset
I
CC1
I
CC2
I
CC2
I
CC2
I
CC3
6
6
6
6
6
6
6
6
6
11.6
7.0
5.0
−
0.6
1.3
1.3
1.3
400
12.6
7.7
5.6
4.0
1.1
1.8
2.2
2.8
680
13.6
8.4
6.2
−
1.8
2.5
3.0
3.3
1000
V
V
V
V
mA
mA
mA
mA
mA
Symbol
Pin
Min
Typ
Max
Unit
Default Internal Setpoint for Skip Cycle Operation and Standby
Detection
Default Internal Setpoint to Leave Standby
Propagation Delay from CS Detected to Gate Turned Off (V
Gate
= 10 V)
(Pin 5 Loaded by 1.0 nF)
Leading Edge Blanking Duration
Soft−Start Period (Note 3)
Temperature Shutdown, Maximum Value (Note 3)
Hysteresis while in Temperature Shutdown (Note 3)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Verified by Design.
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