Quad-Frequency Programmable
VCXO
IDT8N0QV01 Rev G
Preliminary Data Sheet
General Description
The 8N0QV01 is a Quad-Frequency Programmable VCXO with very
flexible frequency and pull-range programming capabilities. The
device uses IDT’s Fourth Generation FemtoClock® NG technology
for an optimum of high clock frequency and low phase noise
performance (0.75ps, RMS 12kHz - 20MHz). The device accepts
2.5V or 3.3V supply and is packaged in a small, lead-free (RoHS 6)
10-lead ceramic 5mm x 7mm x 1.55mm package.
Besides the four default power-up frequencies set by the FSEL0
and FSEL1 pins, the 8N0QV01 can be programmed via the I
2
C
interface to any output clock frequency between 15.476MHz to
260MHz to a very high degree of precision with a frequency step
size of 435.9Hz ÷N (N: PLL post divider). Since the FSEL0 and
FSEL1 pins are mapped to four independent PLL, P, M and N
divider registers (P, MINT, MFRAC and N), reprogramming those
registers to other frequencies under control of FSEL0 and FSEL1 is
supported. The extended temperature range supports wireless
infrastructure, telecommunication and networking end equipment
requirements.
Features
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Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
260MHz
Four power-up default frequencies (see part number order
codes), re-programmable by I
2
C
I
2
C programming interface for the output clock frequency, APR
and internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
Absolute pull-range (APR) programmable from ±2.5 to
±727.5ppm
One 2.5V, 3.3V LVCMOS clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.75ps
(typical)
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 1ps (typical)
2.5V or 3.3V supply voltage modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Block Diagram
OSC
114.285 MHz
÷MINT,
MFRAC
2
VC
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pin Assignment
÷P
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Q
VC 1
OE 2
GND 3
FSEL0 4
FSEL1 5
10 SCLK
9 SDATA
8 V
DD
7 DNU
6 Q
A/D
7
25
Configuration Register (ROM)
(Frequency, APR, Polarity)
I
2
C Control
7
IDT8N0QV01 Rev G
10-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice
IDT8N0QV01GCD
REVSION A APRIL 11, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N0QV01 Rev G Preliminary Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Block Diagram with Programming Registers
PFD
&
LPF
Output Divider N
FemtoClock® NG
VCO
1950-2600MHz
÷
N
OSC
114.285 MHz
2
÷P
Feedback Divider M (25 Bit)
MINT
(7 bits)
MFRAC
(18 bits)
7
VC
A/D
7
7
18
34
41
Programming Registers
ADC_GAIN
ADC_POL
1 bit
1 bit
MINT0
7 bits
7 bits
MINT1
7 bits
7 bits
MINT2
7 bits
7 bits
MINT3
7 bits
7 bits
MFRAC0
18 bits
18 bits
MFRAC1
18 bits
18 bits
MFRAC2
18 bits
18 bits
MFRAC3
18 bits
18 bits
N0
7 bits
7 bits
N1
7 bits
7 bits
N2
7 bits
7 bits
N3
7 bits
7 bits
34
34
34
34
I C Control
7
2
I
2
C:
Def:
6 bits
6 bits
P0
7
I
2
C:
30
Def:
2 bits
2 bits
P1
00
I
2
C:
30
Def:
2 bits
2 bits
P2
01
SCLK
SDATA
Pullup
Pullup
I
2
C:
30
Def:
2 bits
2 bits
P3
34
10
I
2
C:
30
Def:
2 bits
2 bits
11
FSEL[1:0]
OE
Pulldown, Pulldown
Pullup
Def: Power-up default register setting for I
2
C registers
ADC_GAINn, ADC_POL, Pn, MINTn, MFRACn and Nn
IDT8N0QV01GCD
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©2012 Integrated Device Technology, Inc.
IDT8N0QV01 Rev G Preliminary Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
5, 4
6
7
8
9
10
Name
VC
OE
GND
FSEL1, FSEL0
Q
DNU
V
DD
SDATA
SCLK
Power
Input
Input
Pullup
Pullup
Input
Input
Power
Input
Output
Pulldown
Pullup
Type
Description
VCXO Control Voltage. The control voltage versus frequency characteristics are
set by the ADC_GAIN[5:0] register bits. (see Table 3C).
Output enable pin. See Table 3B for function. LVCMOS/LVTTL interface levels.
Power supply ground.
Default frequency select pins. See Table 3A for function and Tables 8 and 9 for
the default frequency order codes. LVCMOS/LVTTL interface levels.
Clock output. LVCMOS/LVTTL interface levels.
Do not use.
Positive power supply.
I
2
C Data Input. LVCMOS/LVTTL interface levels.
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
VC
Power Dissipation
Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Q
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.465V or 2.625V
10
8
50
50
15
19
pF
pF
k
Ω
k
Ω
Test Conditions
FSEL[1:0], SDATA, SCLK
Minimum
Typical
3.5
Maximum
Units
pF
Ω
Ω
IDT8N0QV01GCD
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©2012 Integrated Device Technology, Inc.
IDT8N0QV01 Rev G Preliminary Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Function Tables
Table 3A. Default Frequency Selection
Input
FSEL1
0 (default)
0
1
1
FSEL0
0 (default)
1
0
1
Operation
Default frequency 0.
Default frequency 1.
Default frequency 2.
Default frequency 3.
NOTE: The default frequency is the output frequency after power-up. One of four default
frequencies is selected by FSEL[1:0]. See programming section for details.
Table 3B. OE Configuration
Input
OE
0
1 (default)
Output Enable
Output Q are in high-impedance state.
Outputs are enabled.
NOTE: OE is an asynchronous control.
IDT8N0QV01GCD
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©2012 Integrated Device Technology, Inc.
IDT8N0QV01 Rev G Preliminary Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Principles of Operation
The block diagram consists of the internal 3
RD
overtone crystal and
oscillator which provide the reference clock f
XTAL
of 114.285MHz.
The PLL includes the FemtoClock NG VCO along with the pre-divider
(P), the feedback divider (M) and the post divider (N). The
P, M,
and
N
dividers determine the output frequency based on the f
XTAL
reference and must be configured correctly for proper operation. The
feedback divider is fractional supporting a huge number of output
frequencies. The configuration of the feedback divider to integer-only
values results in an improved output phase noise characteristics at
the expense of the range of output frequencies. In addition, internal
registers are used to hold up to four different factory pre-set
P, M,
and
N
configuration settings.
These
default pre-sets are stored in the I
2
C
registers at power-up. Each configuration is selected via the the
FSEL[1:0] pins and can be read back using the SCLK and SDATA
pins.
The user may choose to operate the device at an output frequency
different than that set by the factory. After power-up, the user may
write new P, N and M settings into one or more of the four
configuration registers and then use the FSEL[1:0] pins to select the
newly programmed configuration. Note that the I
2
C registers are
volatile and a power supply cycle will reload the pre-set factory
default conditions.
If the user does choose to write a different
P, M,
and
N
configuration,
it is recommended to write to a configuration which is not currently
selected by FSEL[1:0] and then change to that configuration after the
I
2
C
transaction has completed. Changing the FSEL[1:0] controls
results in an immediate change of the output frequency to the
selected register values. The
P, M,
and
N
frequency configurations
support an output frequency range 15.476MHz to 260MHz.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency f
OUT
is
calculated by:
1
f OUT
=
f XTAL
⋅
------------
⋅
MINT
+
MFRAC
+ 0.5
------------------------------------
-
P
⋅
N
18
2
The four configuration registers for the
P, M (MINT & MFRAC)
and
N
dividers which are named Pn, MINTn, MFRACn and Nn with n = 0 to
3. “n” denominates one of the four possible configurations.
As identified previously, the configurations of
P, M (MINT & MFRAC)
and
N
divider settings are stored the I
2
C register, and the
configuration loaded at power-up is determined by the FSEL[1:0]
pins.
Table 4. Frequency Selection
Input
FSEL1
0 (def.)
0
1
1
FSEL0
0 (def.)
1
0
1
Selects
Frequency 0
Frequency 1
Frequency 2
Frequency 3
Register
P0, MINT0, MFRAC0, N0
P1, MINT1, MFRAC1, N1
P2, MINT2, MFRAC2, N2
P3, MINT3, MFRAC3, N3
Frequency Configuration
An order code is assigned to each frequency and VCXO pull range
configuration programmed by the factory (default frequencies). For
more information on the available default frequencies and order
codes, please see the Ordering Information section in this document.
For available order codes, see the
FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Information
document.
For more information and guidelines on programming of the device
for custom frequency configurations, programming for a specific
VCXO pull range, the available APR (absolute pull range), the
register description and the serial interface description, see the
FemtoClock NG Ceramic 5x7 Module Programming Guide.
(1)
IDT8N0QV01GCD
REVSION A APRIL 11, 2012
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©2012 Integrated Device Technology, Inc.
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