Si500D
D
IFFERENTIAL
O
UTPUT
S
I L I C O N
O
SCILLATOR
Features
Quartz-free silicon oscillator
Any-rate output frequencies from 0.9 to 200 MHz
Quick turn delivery
Highly reliable startup and operation
Tri-state or power down operation
1.8, 2.5, or 3.3 V options
LVPECL, LVDS, HCSL, differential CMOS,
and differential SSTL versions available
3.2 x 4.0 mm footprint compatible with
industry-standard 3.2 x 5.0 mm pinout
Low power
Pb-free and RoHS compliant
Specifications
Parameters
Frequency Range
Frequency Stability
Operating Temperature
Storage Temperature
Supply Voltage
Condition
See Note 1.
Min
0.9
—
0
–55
1.71
2.25
2.97
—
—
—
—
—
—
—
—
—
—
46 – 13 ns/T
CLK
—
—
—
V
DD
– 1.5
.720
—
.68
1.15
0.25
0.85
0.25
0.35
0.65
45
V
DD
– 0.6
—
.5 x V
DD
+ 0.375
.5 x V
DD
+ 0.48
.45 x V
DD
+ 0.48
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
34.0
19.3
14.9
25.3
29.0
24.5
24.3
22.2
9.7
1.0
—
—
—
1.1
—
—
N/A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
0.6
0.7
Max
200
±150
+70
+125
1.98
2.75
3.63
36.0
22.2
16.5
29.3
31.8
27.7
26.7
25
10.7
1.9
54 + 13 ns/T
CLK
460
800
1.6
V
DD
– 1.34
.880
—
.95
1.26
0.45
0.96
0.45
.425
.82
55
—
0.6
.5 x V
DD
– 0.375
.5 x V
DD
– 0.48
.45 V
DD
– 0.48
2
250 + 3 x T
CLK
250 + 3 x T
CLK
12 + 3 x T
CLK
2
2
3
1
1.5
Units
MHz
ppm
C°
C°
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
%
ps
ps
ns
V
V
PK
V
V
PK
V
V
PK
V
V
PK
V
V
PK
Ω
V
V
V
V
V
ms
ns
ns
µs
ms
ps RMS
ps RMS
ps RMS
ps RMS
Supply Current
Output Symmetry
Rise and Fall Times (20/80%)
2
LVPECL Output Option
(DC coupling, 50
Ω
to V
DD
– 2.0 V)
2
Low Power LVPECL Output Option
(AC coupling, 100
Ω
Differential Load)
2
LVDS Output Option (2.5/3.3 V)
(R
TERM
= 100
Ω
diff)
2
LVDS Output Option (1.8 V)
(R
TERM
= 100
Ω
diff)
2
HCSL Output Option
2
CMOS Output Voltage
2
SSTL Output Voltage
2
Powerup Time
OE Deassertion to Clk Stop
Return from Output Driver Stopped Mode
Return From Tri-State Time
Return From Powerdown Time
Period Jitter (1-sigma)
Integrated Phase Jitter
1.8 V option
2.5 V option
3.3 V option
LVPECL
Low Power LVPECL
LVDS
HCSL
Differential CMOS(3.3 V option,10 pF,200 MHz)
Differential SSTL-3
Differential SSTL-2
Differential SSTL-18
Tri-State
Powerdown
V
DIFF
= 0
LVPECL/LVDS
HCSL/Differential SSTL
Differential CMOS, 15 pF, >80 MHz
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
DC termination per pad
V
OH
, sourcing 9 mA
V
OL
, sinking 9 mA
SSTL-18
SSTL-2
SSTL-3
From time V
DD
crosses min spec supply
Non-CMOS
CMOS, C
L
= 7 pF
1.0 MHz – min(20 MHz, 0.4 x F
OUT
),non-CMOS
1.0 MHz – min(20 MHz, 0.4 x F
OUT
),CMOS format
Notes:
1.
Inclusive of 25 C° initial frequency accuracy, operating temperature range, supply voltage change, output load change, 1st year aging at
25 C°, shock and vibration.
2.
See AN409 for further details regarding output clock termination recommendations. SSTL minimum output voltage is minimum V
OH
. SSTL
maximum output voltage is maximum V
OL
.
Rev. 0.2 9/08
Copyright © 2008 by Silicon Laboratories
Si500D
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si500D
Package Specifications
Table 1. Package Diagram Dimensions (mm)
Dimension
Min
Nom
Max
Dimension
Min
Nom
Max
A
A1
b
D
e
E
L
0.80
0.00
0.59
3.20 BSC.
1.27 BSC.
4.00 BSC.
0.95
0.85
0.03
0.64
0.90
0.05
0.69
L1
aaa
bbb
ccc
ddd
eee
0.00
—
—
—
—
—
0.05
—
—
—
—
—
0.10
0.10
0.10
0.08
0.10
0.05
1.00
1.05
Table 2. Pad Connections
1
2
3
4
5
6
OE
NC—Make no external
connection to this pin
GND
Output
Complementary Output
VDD
Table 3. Tri-State/Powerdown/Driver Stopped
Function on OE (3rd Option Code)
A
Open
1
Level
0
Level
Active
Active
Tri-
State
B
Active
Tri-
State
Active
C
Active
Active
Power-
down
D
Active
Power-
down
Active
E
Active
Active
Driver
Stopped
F
Active
Driver
Stopped
Active
0 C CC CC
T TTT TT
Dimension
C1
E
X1
Y1
(mm)
2.70
1.27
0.75
1.55
Y Y WW
0 = Si500
CCCCC = mark code
TTTTTT = assembly manufacturing code
YY = year
WW = work week
Figure 2. Top Mark
Figure 1. Recommended Land Pattern
2
Rev. 0.2
Si500D
Environmental Compliance
Parameter
Conditions/Test Method
Mechanical Shock
Mechanical Vibration
Resistance to Soldering Heat
Solderability
Damp Heat
Moisture Sensitivity Level
MIL-STD-883, Method 2002.4
MIL-STD-883, Method 2007.3 A
MIL-STD-202, 260 C
°
for 8 seconds
MIL-STD-883, Method 2003.8
IEC 68-2-3
J-STD-020, MSL 3
Ordering Information
The Si500D supports a variety of options including frequency, output format, supply voltage, and tri-
state/powerdown. Specific device configurations are programmed into the Si500D at time of shipment.
Configurations are specified using the figure below. Silicon Labs provides a web-based part number utility that can
be used to simplify part number configuration. Refer to www.silabs.com/XOPartNumber to access this tool. The
Si500D XO series is supplied in a ROHS-compliant, Pb-free, 6-pad, 3.2 x 4.0 mm package. Tape and reel
packaging is available as an ordering option.
500D
Si500
Differential
Oscillator
X
X
X
XXMXXXX
Frequency
xMxxxxx: f
OUT
< 10 MHz
xxMxxxx: 10 MHz < f
OUT
< 100 MHz
xxxMxxx: f
OUT
> 100 MHz
3
rd
Option Code
Tri-State/Powerdown/
Output Driver Stopped
A
OE active high/tristate
B
OE active low/tristate
C
OE active high/powerdown
D
OE active low/powerdown
E
OE active high/driver stopped
F
OE active low/driver stopped
2
nd
Option Code
A
Stability (ppm, max)
±150
A
B
F
R
R = Tape & Reel
Blank = Tubes
1
st
Option Code
V
DD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
1.8
1.8
1.8
1.8
1.8
1.8
Format
LVPECL
Low Power LVPECL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
LVPECL
Low Power LVPECL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
Oper. Temp Range (degC)
F
0 to 70 deg C
Product Revision = B
Package
A
3.2 x 4.0 mm SMD
Rev. 0.2
3
Si500D
C
ONTACT
I
NFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: XOinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
4
Rev. 0.2
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