PRELIMINARY
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-
TO-LVDS FANOUT BUFFER
ICS854210
G
ENERAL
D
ESCRIPTION
The ICS854210 is a low skew, high performance
dual 1-to- 5 Differential-to-LVDS Fanout Buffer
HiPerClockS™
and a member of the HiPerClockS™ family of
High Perfor mance Clock Solutions from IDT.
The ICS85 4210 is character ized to operate
from a 3.3V power supply. Guaranteed output and par t-
to-par t skew characteristics make the ICS854210 ideal for
t h o s e c l o c k d i s t r i b u t i o n a p p l i c a t i o n s d e m a n d i n g we l l
defined perfor mance and repeatability.
F
EATURES
•
Two differential LVDS bank outputs
•
Two differential LVPECL clock input pairs
•
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•
Maximum output frequency: 2GHz
•
Translates any single ended input signal to
LVDS levels with resistor bias on nPCLKx input
•
Output skew: TBD
•
Part-to-part skew: TBD
•
Propagation delay: 280ps (typical)
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
nQA3
nQA4
nQB0
nQB1
QA3
QA4
QB0
QB1
PCLKA
nPCLKA
Pulldown
Pullup/Pulldown
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
24 23 22 21 20 19 18 17
V
DDO
nQA2
QA2
nQA1
QA1
nQA0
QA0
V
DDO
25
26
27
28
29
30
31
32
1
V
DD
16
15
14
V
DDO
QB2
nQB2
QB3
nQB3
QB4
nQB4
V
DDO
ICS854210
13
12
11
10
9
2
nc
3
PCLKA
4
nPCLKA
5
nc
6
PCLKB
7
nPCLKB
8
GND
PCLKB
nPCLKB
Pulldown
Pullup/Pulldown
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
LVDS FANOUT BUFFER
1
ICS854210CY REV. C MAY 6, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 5
3
4
6
7
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
Name
V
DD
nc
PCLKA
nPCLKA
PCLKB
nPCLKB
GN D
V
DDO
nQB4, QB4
nQB3, QB3
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
Power
Unused
Input
Input
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Description
Power supply pin.
No connect.
Pulldown Non-inver ting differential LVPECL clock input.
Pullup/ Inver ting differential LVPECL clock input.
Pulldown V
DD
/2 default when left floating.
Pulldown Non-inver ting differential LVPECL clock input.
Pullup/ Inver ting differential LVPECL clock input.
Pulldown V
DD
/2 default when left floating.
Power supply ground.
Output supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
VDD/2
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
kΩ
kΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
PCLKA or PCLKB
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nPCLKA or nPCLKB
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
QA0:QA4,
nQA0:nQA4,
QB0:QB4
nQB0:nQB4
LOW
HIGH
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
IDT
™
/ ICS
™
LVDS FANOUT BUFFER
2
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Negative Supply Voltage, V
EE
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
(Junction-to-Ambient)
4.6V
-4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
-65°C to 150°C
NOTE:
Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These rat-
ings are stress specifications only. Functional operation of prod-
uct at these conditions or any conditions beyond those listed in
the
DC Characteristics
or
AC Characteristics
is not implied. Ex-
posure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
Operating Temperature Range, T
A
-40°C to +85°C
Package Thermal Impedance,
θ
JA
47.9°C/W (0 lfpm)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
TBD
TBD
Maximum
3.465
3.465
Units
V
V
mA
mA
T
ABLE
4B. LVPECL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
I
IH
I
IL
V
TH
V
TL
V
PP
Input High Current
Input Low Current
PCLKA, PCLKB
nPCLKA, nPCLKB
PCLKA, PCLKB
nPCLKA, nPCLKB
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-10
100
-100
0.15
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
mV
mV
V
V
Differential Input High Threshold Voltage
Differential Input Low Threshold Voltage
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
GND + 1.2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLKA, nPCLKA and PCLKB, nPCLKB
is V
DD
+ 0.3V.
IDT
™
/ ICS
™
LVDS FANOUT BUFFER
3
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.25
50
-40°C
Min
Typ
Max
Min
25°C
Typ
35 0
50
Max
Min
85°C
Typ
Ma x
Units
mV
mV
V
mV
NOTE 1: Refer to Parameter Measurement Information, "3.3V Output Load Test Circuit" diagram.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
20% to 80%
-40°C
Min
Typ
2
26 0
TBD
TBD
175
Max
Min
25°C
Typ
2
280
TB D
TBD
180
Max
Min
85°C
Typ
2
305
TBD
TBD
190
Max
Units
GHz
ps
ps
ps
ps
t
PD
t
sk(o)
t
sk(pp)
t
R
/t
F
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
LVDS FANOUT BUFFER
4
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
DD
SCOPE
3.3V±5%
POWER SUPPLY
+ Float GND –
V
DD,
V
DDO
Qx
V
LVDS
nQx
PP
Cross Points
V
CMR
GND
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQx
Qx
nQy
Qy
tsk(o)
D
IFFERENTIAL
I
NPUT
L
EVEL
nQx
PART 1
Qx
nQy
PART 2
Qy
tsk(pp)
O
UTPUT
S
KEW
V
DD
out
➤
P
ART
-
TO
-P
ART
S
KEW
V
DD
➤
➤
out
DC Input
LVDS
out
➤
DC Input
LVDS
➤
100
V
OD
/Δ V
OD
out
➤
V
OS
/Δ V
OS
V
OS
S
ETUP
nQAx,
nQBx
80%
80%
V
OD
QAx,
QBx
20%
t
R
t
F
20%
V
OD
S
ETUP
nPCLKA,
nPCLKB
PCLKA,
PCLKB
nQAx,
nQBx
QAx,
QBx
t
PD
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
IDT
™
/ ICS
™
LVDS FANOUT BUFFER
5
ICS854210CY REV. C APRIL 7, 2008
ADI Reference Circuit
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