65
CY7C265
8K x 8 Registered PROM
Features
• CMOS for optimum speed/power
• High speed (commercial and military)
— 15 ns address set-up
— 12 ns clock to output
• Low power
— 660 mW (commercial)
— 770 mW (military)
• On-chip edge-triggered registers
— Ideal for pipelined microprogrammed systems
• EPROM technology
— 100% programmable
— Reprogrammable (7C265W)
• 5V
±10%
V
CC
, commercial and military
• Capable of withstanding >2001V static discharge
• Slim 28-pin, 300-mil plastic or hermetic DIP
are enabled. One pin on the CY7C265 is programmed to per-
form either the enable or the initialize function.
If the asynchronous enable (E) is being used, the outputs may
be disabled at any time by switching the enable to a logic
HIGH, and may be returned to the active state by switching the
enable to a logic LOW.
If the synchronous enable (ES) is being used, the outputs will
go to the OFF or high-impedance state upon the next positive
clock edge after the synchronous enable input is switched to a
HIGH level. If the synchronous enable pin is switched to a logic
LOW, the subsequent positive clock edge will return the output
to the active state. Following a positive clock edge, the address
and synchronous enable inputs are free to change since no
change in the output will occur until the next LOW-to-HIGH
transition of the clock. This unique feature allows the CY7C265
decoders and sense amplifiers to access the next location
while previously addressed data remains stable on the outputs.
If the E/I pin is used for INIT (asynchronous), then the outputs
are permanently enabled. The initialize function is useful dur-
ing power-up and time-out sequences, and can facilitate im-
plementation of other sophisticated functions such as a built-in
“jump start” address. When activated, the initialize control in-
put causes the contents of a user programmed 8193rd 8-bit
word to be loaded into the on-chip register. Each bit is pro-
grammable and the initialize function can be used to load any
desired combination of 1’s and 0’s into the register. In the un-
programmed state, activating INIT will generate a register
clear (all outputs LOW). If all the bits of the initialize word are
programmed to be a 1, activating INIT performs a register pre-
set (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load of
the programmed initialize word into the pipeline register and
onto the outputs. The INIT LOW disables clock and must return
HIGH to enable clock independent of all other inputs, including
the clock.
Functional Description
The CY7C265 is a 8192 x 8 registered PROM. It is organized
as 8,192 words by 8 bits wide, and has a pipeline output reg-
ister. In addition, the device features a programmable initialize
byte that may be loaded into the pipeline register with the ini-
tialize signal. The programmable initialize byte is the 8,193rd
byte in the PROM and its value is programmed at the time of
use.
Packaged in 28 pins, the PROM has 13 address signals (A
0
through A
12
), 8 data out signals (O
0
through O
7
), E/I (enable
or initialize), and CLOCK.
CLOCK functions as a pipeline clock, loading the contents of
the addressed memory location into the pipeline register on
each rising edge. The data will appear on the outputs if they
Cypress Semiconductor Corporation
Document #: 38-04012 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised March 14, 2002
CY7C265
Logic Block Diagram
Pin Configurations
DIP/Flatpack
Top View
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
5
A
4
A
3
A
2
A
1
A
0
CLK
PROGRAMMABLE
MULTIPLEXER
COLUMN
ADDRESS
ADDRESS
DECODER
ROW
ADDRESS
PROGRAMMABLE
ARRAY
COLUMN
MULTIPLEXER
O
7
A
7
A
6
A
5
A
4
A
3
A
2
GND
CLK
A
1
A
0
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
7C265
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A
8
A
9
A
10
A
11
A
12
E/E
S
,I
GND
GND
O
7
O
6
O
5
O
4
O
3
O
6
O
5
PROGRAMMABLE
INITIALIZE WORD
8-BIT
EDGE-
TRIGGERED
REGISTER
O
4
O
3
O
2
O
1
O
0
LCC/PLCC (Opaque Only)
Top View
A
4
A
5
A
6
A
7
V
CC
A
8
A
9
4
3
2 1 28 27 26
25
24
23
22
21
20
19
12 13 14 15 16 17 18
O
1
O
2
GND O
3
O
4
O
5
O
6
A
10
A
11
A
12
E/E
S
,I
GND
GND
O
7
INIT/E/E
S
CLK
D
C
O
A
3
A
2
GND
CLK
A
1
A
0
O
0
5
6
7
8
9
10
11
F
Selection Guides
7C265–15
Minimum Address Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum Operating Current (mA)
Com’l
Mil
15
12
120
140
7C265–25
25
15
120
140
7C265–40
40
20
100
7C265–50
50
25
80
120
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
DC Program Voltage .....................................................13.0V
UV Exposure.................................................7258 Wsec/cm
2
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Military
[2]
[1]
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C
V
CC
5V
±10%
5V
±10%
5V
±10%
Notes:
1. Contact a Cypress representative for industrial temperature range spec-
ifications.
2. T
A
is the “instant on” case temperature.
Document #: 38-04012 Rev. **
Page 2 of 13
CY7C265
Electrical Characteristics
Over the Operating Range
[3]
7C265-15, 25
Parameter
V
OH
V
OL
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
V
CC
= Min., I
OH
= –2.0 mA
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA Com’l
V
CC
= Min., I
OL
= 12.0 mA
V
CC
= Min., I
OL
= 6.0 mA Mil
V
CC
= Min., I
OL
= 8.0 mA
V
IH
V
IL
I
IX
I
OZ
I
OS[4]
I
CC
V
PP
I
PP
V
IHP
V
ILP
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Output Short Circuit Current
V
CC
Operating Supply
Current
Programming Supply Voltage
Programming Supply Current
Input HIGH Programming
Voltage
Input LOW Programming
Voltage
3.0
0.4
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max., I
OUT
= 0 mA Com’l
Mil
12
–10
–40
2.0
0.8
+10
+40
90
120
140
13
50
3.0
0.4
12
13
50
3.0
0.4
12
–10
–40
2.0
0.8
+10
+40
90
100
–10
–40
2.0
0.8
+10
+40
90
80
120
13
50
V
mA
V
V
0.4
0.4
V
V
µA
µA
mA
mA
0.4
0.4
0.4
Min.
2.4
2.4
2.4
V
7C265-40
7C265-50
V
Max. Min. Max. Min. Max. Unit
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
10
Unit
pF
pF
Notes:
3. See the last page of this specification for Group A subgroup testing information.
4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
5. See Introduction to CMOS PROMs in this Data Book for general information on testing.
Document #: 38-04012 Rev. **
Page 3 of 13
CY7C265
AC Test Loads and Waveforms
Test Load for -15 through -25 speeds
R1 500
(658
Ω
MIL)
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
R2 333
Ω
(403
Ω
MIL)
5 pF
INCLUDING
JIG AND
SCOPE
R2 333
Ω
(403
Ω
MIL)
R1 500
Ω
(658
Ω
MIL)
3.0V
GND
90%
10%
90%
10%
≤
5 ns
≤
5 ns
(a) NormalLoad
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
R
TH
200
Ω
250
Ω
MIL
(b) High Z Load
Test Load for -40 through -50 speeds
R1 250
Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
R2 167
Ω
5 pF
INCLUDING
JIG AND
SCOPE
R2 167
Ω
R1 250
Ω
(c) Normal Load
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
100
Ω
OUTPUT
2.0V
(d) High Z Load
Switching Characteristics
Over the Operating Range
[3, 5]
7C265-15
Parameter
t
AS
t
HA
t
CO
t
PWC
t
SES
t
HES
t
DI
t
RI
t
PWI
t
COS
t
HZC
t
DOE
t
HZE
Description
Address Set-Up to Clock
Address Hold from Clock
Clock to Output Valid
Clock Pulse Width
E
S
Set-Up to Clock
(Sync. Enable Only)
E
S
Hold from Clock
INIT to Output Valid
INIT Recovery to Clock
INIT Pulse Width
Output Valid from Clock
(Sync. Mode)
Output Inactive from Clock
(Sync. Mode)
Output Valid from E LOW
(Async. Mode)
Output Inactive from E HIGH
(Async. Mode)
12
12
12
12
12
12
12
12
5
15
15
15
15
15
15
15
Min.
15
0
12
15
15
5
18
20
25
20
20
20
20
Max.
7C265-25
Min.
25
0
15
15
15
5
25
25
35
25
25
25
25
Max.
7C265-40
Min.
40
0
20
20
15
5
35
Max.
7C265-50
Min.
50
0
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-04012 Rev. **
Page 4 of 13
CY7C265
Switching Waveform
ADDRESS
t
AS
SYNCHRONOUS
ENABLE
(PROGRAMMABLE)
t
SES
CLOCK
t
PWC
OUTPUT
t
DI
t
PWI
ASYNCHRONOUS INIT
(PROGRAMMABLE)
t
RI
ASYNCHRONOUS
ENABLE
VALID DATA
t
HZC
t
HZE
t
DOE
t
COS
t
CO
t
HES
t
AH
Erasure Characteristics
Wavelengths of light less than 4000 angstroms begin to erase
the 7C265 in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM
is exposed to sunlight or fluorescent lighting for extended pe-
riods of time.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 angstroms for a minimum dose (UV inten-
sity • exposure time) of 25 Wsec/cm
2
. For an ultraviolet lamp
with a 12 mW/cm
2
power rating the exposure time would be
approximately 45 minutes. The 7C265 needs to be within one
inch of the lamp during erasure. Permanent damage may re-
sult if the PROM is exposed to high-intensity UV light for an
extended period of time. 7258 Wsec/cm
2
is the recommended
maximum dosage.
Control Byte
00 Asynchronous output enable (default condition)
01 Synchronous output enable
02 Asynchronous initialize
Programming Modes
The 7C265 offers a limited selection of programmed architec-
tures. Programming these features should be done with a sin-
gle 10-ms-wide pulse in place of the intelligent algorithm,
mainly because these features are verified operationally, not
with the VFY pin. Architecture programming is implemented by
applying the supervoltage to two additional pins during pro-
gramming. In programming the 7C265 architecture, VPP is ap-
plied to pins 3, 9, and 22. The choice of a particular mode
depends on the states of the other pins during programming,
so it is important that the condition of the other pins be met as
set forth in the mode table. The considerations that apply with
respect to power-up and power-down during intelligent pro-
gramming also apply during architecture programming. Once
the supervoltages have been established and the correct logic
states exist on the other device pins, programming may begin.
Programming is accomplished by pulling PGM from HIGH to
LOW and then back to HIGH with a pulse width equal to 10 ms.
Bit Map Data
Programmer Address (Hex.)
Decimal
0
.
.
8191
8192
8193
Hex
0
.
.
1FFF
2000
2001
RAM Data
Contents
Data
.
.
Data
INIT Byte
Control Byte
Document #: 38-04012 Rev. **
Page 5 of 13
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