XDR
™
DRAM
8x16Mx4
Advance Information
Overview
The Rambus XDR
™
DRAM device is a general-purpose high-
performance memory device suitable for use in a broad range
of applications, including computer memory, graphics, video,
and any other application where high bandwidth and low
latency are required.
The 512Mb Rambus XDR DRAM device is a CMOS DRAM
organized as 128M words by 4 bits. The use of Differential
Rambus Signaling Level (DRSL) technology permits 4000/
3200/2400 Mb/s transfer rates while using conventional sys-
tem and board design technologies. XDR DRAM devices are
capable of sustained data transfers of 2000/1600/1200 MB/s.
XDR DRAM device architecture allows the highest sustained
bandwidth for multiple, interleaved randomly addressed mem-
ory transactions. The highly-efficient protocol yields over 95%
utilization while allowing fine access granularity. The device’s
eight banks support up to four interleaved transactions.
XDR DRAM CSP x4 Pinout
L
1
2
3
4
5
6
7
8
Column
9
10
11
12
13
14
15
16
DQN3
DQ3
DQN15
DQ15
K
DQN9
DQ9
J
VDD
VDD
H
G
F
Row
E
GND
D
VDD
C
B
A
1
2
GND
3
VDD
4
5
6
SDI
GND
7
DQN8 DQN2
DQ8
DQ2
P
DQ5
DQN5
DQN5 VDD RQ10
N
CFM
RSRV
RSRV
VDD
DQN7 RQ0 DQN4
DQ7
RQ4
DQN14
VTERM GND
GND DQ4
RQ3
DQN3 VTERM VDD
DQ3
DQ14
VDD
GND
GND
VDD
DQ5 GND RQ11 CFMN
DQ1
DQN1
VDD VTERM
GND
RQ10
GND VTERM GND
VDD
VDD
VREF
GND
RQ8
RQ6
RQ4
RQ2
VDD
GND
VDD
RQ7
RQ6
GND
GND
M
VDD
L
K
J
H
G
F
E
D
C
B
A
GND
VDD
RQ11
GND
VDD VTERM GND
RQ9
RQ7
CFMN
RQ5
VDD
GND
CFM
GND
GND
VDD
VDD
RQ0 GND
VTERM GND
GND
RST
GND GND
SD0
CMD
RQ9
DQN13 VDD
DQ0
DQN0
DQ13 CMD
RQ8
GND
RQ3
VDD
VDD GND VTERM GND
RQ1
GND
GND
GND
VDD
DQN7
DQ7
VREF
RQ5
SCK
RQ1
SD1
VDD DQN12 DQN6
DQ6
DQN2
DG2
RQ2
GND DQ12
VTERM
GND
VDD
DQN11 DQN1 SCK
DQ11
DQ4
DQN4
GND
DQ1
VDD
VDD
GND
GND
RST DQN0 DQN10
DQ10
Features
•
Highest pin bandwidth available
4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling
• Bi-directional differential RSL (DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
• Programmable on-chip termination
-Adaptive impedance matching
-Reduced system cost and routing complexity
Highest sustained bandwidth per DRAM device
• 2000/1600/1200 MB/s sustained data rate
• Eight banks: bank-interleaved transactions at full
bandwidth
• Dynamic request scheduling
• Early-read-after-write support for maximum efficiency
• Zero overhead refresh
Low latency
• 2.0/2.5/3.33 ns request packets
• Point-to-point data interconnect for fastest possible
flight time
• Support for low-latency, fast-cycle cores
Low power
• 1.800 volt Vdd
• Programmable small-swing I/O signaling (DRSL)
• Low power PLL/DLL design
• Powerdown self-refresh support
• Per pin I/O powerdown for narrow-width operation
DQN6
DQ6
VDD
SDO
DQ0
A16
A8
A4
optional ball
Top view of package
Key Timing Parameters/Part Numbers
Organization
a
Bandwidth
(1/t
BIT
)
b
Latency
(t
RAC
)
c
Bin
d,e
Part Number
8x4Kx4Kx4
8x4Kx4Kx4
8x4Kx4Kx4
8x4Kx4Kx4
8x4Kx4Kx4
8x4Kx4Kx4
2400
3200
3200
4000
3200
4000
36
27
35
28
35
28
A
A
B
B
C
C
8x16Mx4-2400A-36
8x16Mx4-3200A-27
8x16Mx4-3200B-35
8x16Mx4-4000B-28
8x16Mx4-3200C-35
8x16Mx4-4000C-28
•
•
a. Bank x Row x Column x Width
b. Data rate measured in Mbit/s per DQ differential pair. See “Timing Conditions” on page 59
and “Timing Characteristics” on page 62. Note that t
BIT
=t
CYCLE
/8.
c. Read access time t
RAC
(= t
RCD-R
+t
CAC
) measured in ns. See “Timing Parameters” on page 62.
d. Timing parameter bin. See “Timing Parameters” on page 62. This is a measure of the number
of interleaved read transactions needed for maximum efficiency (the value Ceiling(t
RC-R
/t
RR-D
).
For bin A, t
RC-R
/t
RR-D
=4, and for bin B, t
RC-R
/t
RR-D
=5.
e. Bin support is vendor dependent - Some bins may not be supported by some DRAM vendors.
•
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XDR DRAM 8x16Mx4
General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device
write and read transactions. There are three sets of pins used
for normal memory access transactions: CFM/CFMN clock
pins, RQ11..0 request pins, and DQ3..0/DQN3..0 data pins.
The “N” appended to a signal name denotes the complemen-
tary signal of a differential pair.
A
transaction
is a collection of packets needed to complete a
memory access. A
packet
is a set of bit windows on the signals
of a bus. There are two buses that carry packets: the RQ bus
and DQ bus. Each packet on the RQ bus uses a set of 2 bit-
windows on each signal, while the DQ bus uses a set of 16 bit-
windows on each signal.
In the write transaction shown in Figure 1, a request packet (on
the RQ bus) at clock edge T
0
contains an activate (ACT) com-
Figure 1
XDR DRAM Device Write and Read Transactions
T
0
CFM
CFMN
RQ11..0
ACT WR
a0
a1
WR
a2
mand. This causes row Ra of bank Ba in the memory compo-
nent to be loaded into the sense amp array for the bank. A
second request packet at clock edge T
5
contains a write (WR)
command. This causes the data packet D(a1) at edge T
10
to be
written to column Ca1 of the sense amp array for bank Ba. A
third request packet at clock edge T
7
contains another write
(WR) command. This causes the data packet D(a2) at edge T
12
to be also be written to column Ca2. A final request packet at
clock edge T
14
contains a precharge (PRE) command.
The spacings between the request packets are constrained by
the following timing parameters in the diagram: t
RCD
, t
CC
,
and t
WRP
. In addition, the spacing between the request packets
and data packets are constrained by the t
CWD
parameter. The
spacing of the CFM/CFMN clock edges is constrained by
t
CYCLE
.
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
t
RCD-W
DQ3..0
DQN3..0
t
CC
t
CWD
D(a1)
D(a2)
t
WRP
PRE
a3
t
CYCLE
Transaction a:
WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Write Transaction
T
0
CFM
CFMN
RQ11..0
DQ3..0
DQN3..0
ACT
a0
RD
a1
RD
a2
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
t
RCD-R
t
CC
t
RDP
PRE
a3
Q(a1)
Q(a2)
t
CYCLE
t
CAC
Transaction a:
RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Read Transaction
The read transaction shows a request packet at clock edge T
0
containing an ACT command. This causes row Ra of bank Ba
of the memory component to load into the sense amp array for
the bank. A second request packet at clock edge T
5
contains a
read (RD) command. This causes the data packet Q(a1) at edge
T
11
to be read from column Ca1 of the sense amp array for
bank Ba. A third request packet at clock edge T
7
contains
another RD command. This causes the data packet Q(a2) at
edge T
13
to also be read from column Ca2. A final request
packet at clock edge T
12
contains a PRE command.
The spacings between the request packets are constrained by
the following timing parameters in the diagram: t
RCD
, t
CC
,
and t
RDP
. In addition, the spacing between the request and
data packets are constrained by the t
CAC
parameter.
2
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XDR DRAM 8x16Mx4
Table of Contents
Overview .......................................................................1
Features .........................................................................1
XDR DRAM CSP x4 Pinout ........................................... 1
Key Timing Parameters/Part Numbers ......................... 1
General Description ......................................................2
Table of Contents ..........................................................3
List of Tables ................................................................3
List of Figures ...............................................................4
Pin Description .............................................................5
Block Diagram ..............................................................6
Request Packets ............................................................8
Request Packet Formats .................................................... 8
Request Field Encoding ..................................................10
Request Packet Interactions ...........................................12
Request Interaction Cases ...............................................13
Dynamic Request Scheduling .........................................18
Memory Operations ....................................................20
Write Transactions ...........................................................20
Read Transactions ............................................................22
Interleaved Transactions .................................................24
Read/Write Interaction ...................................................26
Propagation Delay ............................................................26
Register Operations ....................................................30
Serial Transactions ...........................................................30
Serial Write Transaction ..................................................30
Serial Read Transaction ...................................................30
Register Summary ............................................................32
Maintenance Operations ............................................40
Refresh Transactions .......................................................40
Interleaved Refresh Transactions ..................................40
Calibration Transactions ................................................. 42
Power State Management ............................................... 44
Initialization ...................................................................... 46
XDR DRAM Initialization Overview ........................... 47
XDR DRAM Pattern Load with WDSL Reg .............. 48
Special Feature Description ....................................... 50
Dynamic Width Control ................................................. 50
Write Masking .................................................................. 52
Multiple Bank Sets and the ERAW Feature ................ 54
Simultaneous Activation ................................................. 56
Simultaneous Precharge .................................................. 57
Operating Conditions ................................................. 58
Electrical Conditions ....................................................... 58
Timing Conditions ........................................................... 59
Operating Characteristics .......................................... 60
Electrical Characteristics ................................................. 60
Supply Current Profile .................................................... 61
Timing Characteristics ..................................................... 62
Timing Parameters ........................................................... 62
Receive/Transmit Timing ......................................... 64
Clocking ............................................................................ 64
RSL RQ Receive Timing ................................................ 65
DRSL DQ Receive Timing ............................................ 66
DRSL DQ Transmit Timing .......................................... 68
Serial Interface Receive Timing ..................................... 70
Serial Interface Transmit Timing ................................... 71
Package Description .................................................. 72
Package Parasitic Summary ............................................ 72
Package Mechanical Drawing ........................................ 74
Package Pin Numbering ................................................. 75
List of Tables
Pin Description .............................................................5
Request Field Description ............................................8
OP Field Encoding Summary .................................... 10
ROP Field Encoding Summary .................................. 10
POP Field Encoding Summary .................................. 11
XOP Field Encoding Summary .................................. 11
Packet Interaction Summary ...................................... 12
SCMD Field Encoding Summary ...............................30
Initialization Timing Parameters ...............................47
XDR DRAM WDSL-to-Core/DQ/SC Map (First Genera-
tion x16/x8/x4 XDR DRAM , BL=16) ....................... 48
Core Data Word-to-WDSL Format ............................ 49
Electrical Conditions .................................................. 58
Timing Conditions ..................................................... 59
Electrical Characteristics ............................................ 60
Supply Current Profile ................................................ 61
Timing Characteristics ............................................... 62
Timing Parameters ..................................................... 62
Package RSL Parasitic Summary ............................... 72
CSP x4 Package Mechanical Parameters ................... 74
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XDR DRAM 8x16Mx4
List of Figures
XDR DRAM Device Write and Read Transactions .....2
512Mb (8x16Mx4) XDR DRAM Block Diagram ..........7
Request Packet Formats ...............................................9
ACT-, RD-, WR-, PRE-to-ACT Packet Interactions .. 14
ACT-, RD-, WR-, PRE-to-RD Packet Interactions .... 15
ACT-, RD-, WR-, PRE-to-WR Packet Interactions ... 16
ACT-, RD, WR-, PRE-to-PRE Packet Interactions ... 17
Request Scheduling Examples ................................... 19
Write Transactions ...................................................... 21
Read Transactions ......................................................23
Interleaved Transactions ............................................25
Write/Read Interaction ..............................................27
Propagation Delay ......................................................29
Serial Write Transaction ............................................. 31
Serial Read Transaction — Selected DRAM .............. 31
Serial Read Transaction — Non-selected DRAM ...... 31
Serial Identification (SID) Register ............................32
Configuration (CFG) Register ....................................33
Power Management (PM) Register ............................33
Write Data Serial Load (WDSL) Control Register .....33
RQ Scan High (RQH) Register .................................34
RQ Scan Low (RQL) Register ....................................34
Refresh Bank (REFB) Control Register .....................34
Refresh High (REFH) Row Register .........................35
Refresh Middle (REFM) Row Register ......................35
Refresh Low (REFL) Row Register ...........................35
IO Configuration (IOCFG) Register ..........................35
Current Calibration 0 (CC0) Register .........................36
Current Calibration 1 (CC1) Register ..........................36
Impedance Calibration 0 (ZC0) Register ..................36
Impedance Calibration 1 (ZC1) Register ....................36
Current Fuse Setting 0 (FZC0) Register .....................37
Current Fuse Setting 1 (FZC1) Register .....................37
Read Only Memory 0 (ROM0) Register .....................37
Read Only Memory 1 (ROM1) Register ..................... 37
TEST Register ............................................................ 38
DLL Register .............................................................. 38
PLL0 Register ............................................................. 38
PLL1 Register ............................................................. 38
IFT Register ............................................................... 39
DA Register ................................................................ 39
Delay (DLY) Control Register ................................... 39
Partner-Definable (PART0-PARTF) Registers ......... 39
Refresh Transactions .................................................. 41
Calibration Transactions ............................................ 43
Power State Management ........................................... 45
Serial Interface System Topology ............................... 46
Initialization Timing for XDR DRAM[k] Device ..... 46
Multiplexers for Dynamic Width Control .................. 50
D-to-S and S-to-Q Mapping for Dynamic Width Control
51
Byte Mask Logic ......................................................... 52
Write-Masked (WRM) Transaction Example ............ 53
Write/Read Interaction — No ERAW Feature ......... 54
Write/Read Interaction — ERAW Feature ............... 54
XDR DRAM Block Diagram with Bank Sets .......... 55
Simultaneous Activation — tRR-D Cases .................. 56
Simultaneous Precharge — tPP-D Cases .................. 57
Clocking Waveforms .................................................. 64
RSL RQ Receive Waveforms ...................................... 65
DRSL DQ Receive Waveforms .................................. 67
DRSL DQ Transmit Waveforms ................................ 69
Serial Interface Receive Waveforms ........................... 70
Serial Interface Transmit Waveforms ......................... 71
Equivalent Circuits for Package Parasitic ................. 73
CSP x4 Package Mechanical Drawing ....................... 74
CSP x4 Package - Pin Numbering (top view) ............ 75
4
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XDR DRAM 8x16Mx4
Pin Description
Table 1 summarizes the pin functionality of the XDR DRAM
device. The first group of pins provide the necessary supply
voltages. These include VDD and GND for the core and inter-
face logic, VREF for receiving input signals, and VTERM for
driving output signals.
The next group of pins are used for high bandwidth memory
accesses. These include DQ3..0 and DQN3..0 for carrying read
Table 1
Pin
Signal
VDD
GND
VREF
VTERM
DQ3..0
DQN3..0
RQ11..0
CFM
CFMN
RST
CMD
SCK
SDI
SDO
RSRV
I/O
-
-
-
-
I/O
I/O
I
I
I
I
I
I
I
O
-
Type
-
-
-
-
DRSL
b
DRSL
b
RSL
b
DIFFCLK
b
DIFFCLK
b
RSL
b
RSL
b
RSL
b
RSL
b
CMOS
b
-
No. of pins
22
a
26
a
1
6
a
4
4
12
1
1
1
1
1
1
1
2
84
and write data signals, RQ11..0 for carrying request signals, and
CFM and CFMN for carrying timing information used by the
DQ, DQN, and RQ signals.
The final set of pins comprise the serial interface that is used
for control register accesses. These include RST for initializing
the state of the device, CMD for carrying command signals,
SDI, and SDO for carrying register read data, and SCK for car-
rying the timing information used by the RST, SDI, SDO, and
CMD signals.
Description
Description
Supply voltage for the core and interface logic of the device.
Ground reference for the core and interface logic of the device.
Logic threshold reference voltage for RSL signals.
Termination voltage for DRSL signals.
Positive data signals that carry write or read data to and from the device.
Negative data signals that carry write or read data to and from the device.
Request signals that carry control and address information to the device.
Clock from master — Positive interface clock used for receiving RSL signals, and
receiving and transmitting DRSL signals from the Channel.
Clock from master — Negative interface clock used for receiving RSL signals,
and receiving and transmitting DRSL signals from the Channel.
Reset input — This pin is used to initialize the device.
Command input — This pin carries command, address, and control register write
data into the device.
Serial clock input — Clock source used for reading from and writing to the con-
trol registers.
Serial data input — This pin carries control register read data through the device.
This pin is also used to initialize the device.
Serial data output — This pin carries control register read data from the device.
This pin is also used to initialize the device.
Reserved pins — Follow Rambus XDR system design guidelines for connecting
RSRV pins
Total pin count per package
a. The exact number of VDD/GND/VTERM pins may vary between XDR DRAM vendors. Vendors may have fewer VDD/GND/VTERM pins
than are shown in this table. For example, balls J6/J11/C6/C11 may not be present in some XDR DRAMs. This table (and the package pin-out dia-
grams) represent a superset across all XDR DRAM vendors.
b. All DQ and CFM signals are high-true; low voltage is logic 0 and high voltage is logic 1.
All DQN, CFMN, RQ, RSL, and CMOS signals are low-true; high voltage is logic 0 and low voltage is logic 1.
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