CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
18-Mbit (512K × 36/1M × 18) Pipelined SRAM
with NoBL™ Architecture (With ECC)
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
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■
Functional Description
The CY7C1370KV33/CY7C1370KVE33/CY7C1372KV33/
CY7C1372KVE33 are 3.3 V, 512K × 36 and 1M × 18
synchronous pipelined burst SRAMs with No Bus Latency™
(NoBL logic, respectively. They are designed to support
unlimited true back-to-back read/write operations with no wait
states. The CY7C1370KV33/CY7C1370KVE33/
CY7C1372KV33/CY7C1372KVE33 are equipped with the
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1370KV33/CY7C1370KVE33/CY7C1372KV33/
CY7C1372KVE33 are pin compatible and functionally equivalent
to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects (BW
a
–
BW
d
for CY7C1370KV33/CY7C1370KVE33 and BW
a
–BW
b
for
CY7C1372KV33/CY7C1372KVE33) and a write enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
Pin-compatible and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
❐
Available speed grades are 250, 200, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte write capability
3.3 V core power supply (V
DD
)
3.3 V/2.5 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
2.5 ns (for 250 MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
165-ball FBGA package
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
On chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
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■
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Selection Guide
Description
Maximum access time
Maximum operating current
× 18
× 36
250 MHz
2.5
180
200
200 MHz
3.0
158
178
167 MHz
3.4
143
163
Unit
ns
mA
Cypress Semiconductor Corporation
Document Number: 001-97836 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 19, 2017
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Logic Block Diagram – CY7C1370KV33
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQ s
DQ P
a
DQ P
b
DQ P
c
DQ P
d
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Logic Block Diagram – CY7C1370KVE33
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
C
C
D
E
C
O
D
E
R
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
DQP
C
DQP
D
E
ECC
ENCODER
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Document Number: 001-97836 Rev. *H
Page 2 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Logic Block Diagram – CY7C1372KV33
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
a
BW
b
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQ s
DQ P
a
DQ P
b
E
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Logic Block Diagram – CY7C1372KVE33
Document Number: 001-97836 Rev. *H
Page 3 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Burst Read Accesses .................................................. 9
Single Write Accesses ................................................. 9
Burst Write Accesses ................................................ 10
Sleep Mode ............................................................... 10
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Partial Write Cycle Description ..................................... 12
Partial Write Cycle Description ..................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 17
3.3 V TAP AC Test Conditions ....................................... 18
3.3 V TAP AC Output Load Equivalent ......................... 18
2.5 V TAP AC Test Conditions ....................................... 18
2.5 V TAP AC Output Load Equivalent ......................... 18
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Identification Codes ....................................................... 19
Boundary Scan Order .................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC®Solutions ....................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Document Number: 001-97836 Rev. *H
Page 4 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
A
A
CE
1
CE
2
BWd
BWc
BWb
BWa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
CE
1
CE
2
NC
NC
BWb
BWa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
A
A
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQPc
DQc
DQc
V
DDQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQPb
DQb
DQb
V
DDQ
V
SS
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
CY7C1370KV33/CY7C1370KVE33
(512K × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
DQb
DQb
NC
V
SS
V
DD
NC
NC
V
DD
V
SS
ZZ
DQb
DQa
DQa
DQb
V
DDQ
V
DDQ
V
SS
V
SS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
V
SS
V
SS
V
DDQ
V
DDQ
NC
DQa
DQa
NC
DQPa
NC
CY7C1372KV33/CY7C1372KVE33
(1M × 18)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC(288)
NC(144)
MODE
A
A
A
A
A
1
A
0
NC(36)
NC(72)
NC(288)
NC(144)
MODE
A
A
A
A
A
1
A
0
NC(72)
NC(36)
V
SS
V
DD
A
A
A
A
A
A
A
Document Number: 001-97836 Rev. *H
V
SS
V
DD
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 5 of 32
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