CY7C1462KV25-200AXCT datasheet, PDF

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CY7C1462KV25-200AXCT: DescriptionSRAM - 同步，SDR 存储器 IC 36Mb（2M x 18）并联 200 MHz 3.2 ns 100-TQFP（14x20）; Categorysemiconductor memory; File Size600KB，32 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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CY7C1462KV25-200AXCT Overview

SRAM - 同步，SDR 存储器 IC 36Mb（2M x 18）并联 200 MHz 3.2 ns 100-TQFP（14x20）

CY7C1462KV25-200AXCT Parametric

Parameter Name	Attribute value
category
Maker	Cypress Semiconductor
series	NoBL™
Package	Tape and Reel (TR)
memory type	Volatile
memory format	SRAM
technology	SRAM - 同步，SDR
storage	36Mb（2M x 18）
memory interface	in parallel
Write cycle time - words, pages	-
Voltage - Power supply	2.375V ~ 2.625V
Operating temperature	0°C ~ 70°C（TA）
Installation type	surface mount type
Package/casing	100-LQFP
Supplier device packaging	100-TQFP（14x20）
Clock frequency	200 MHz
interview time	3.2 ns
Basic product number	CY7C1462

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CY7C1460KV25/CY7C1462KV25

CY7C1460KVE25/CY7C1462KVE25

36-Mbit (1M × 36/2M × 18)

Pipelined SRAM

with NoBL™ Architecture (With ECC)

36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)

Features

■

Functional Description

The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/

CY7C1462KVE25 are 2.5 V, 1M × 36/2M × 18 synchronous

pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic,

respectively. They are designed to support unlimited true

back-to-back read/write operations with no wait states. The

CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/

CY7C1462KVE25 are equipped with the advanced NoBL logic

required to enable consecutive read/write operations with data

being transferred on every clock cycle. This feature dramatically

improves the throughput of data in systems that require frequent

write/read transitions. The CY7C1460KV25/CY7C1462KV25/

CY7C1460KVE25/CY7C1462KVE25 are pin-compatible and

functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the clock enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle. Write operations are controlled by the byte write selects

for

CY7C1460KV25/CY7C1460KVE25

and

–BW

for CY7C1462KV25/CY7C1462KVE25 and a write

enable (WE) input. All writes are conducted with on-chip

synchronous self-timed write circuitry.

Three synchronous chip enables (CE

, CE

) and an

asynchronous output enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Pin-compatible and functionally equivalent to ZBT™

Supports 250 MHz bus operations with zero wait states

❐

Available speed grades are 250 MHz, 200 MHz, and 167 MHz

Internally self-timed output buffer control to eliminate the need

to use asynchronous OE

Fully registered (inputs and outputs) for pipelined operation

Byte Write capability

2.5 V core power supply

2.5 V I/O power supply

Fast clock-to-output times

❐

2.5 ns (for 250 MHz device)

Clock enable (CEN) pin to suspend operation

Synchronous self-timed writes

CY7C1460KV25, CY7C1462KV25, CY7C1460KVE25 and

CY7C1462KVE25 available in JEDEC-standard Pb-free

100-pin TQFP, and Pb-free and non Pb-free 165-ball FBGA

packages.

IEEE 1149.1 JTAG-Compatible Boundary Scan

Burst capability — linear or interleaved burst order

“ZZ” sleep mode option

On-chip error correction code (ECC) to reduce soft error rate

(SER)

■

Selection Guide

Description

Maximum access time

Maximum operating current

× 18

× 36

250 MHz

2.5

220

240

200 MHz

3.2

190

210

167 MHz

3.4

170

190

Unit

Cypress Semiconductor Corporation

Document Number: 001-66679 Rev. *J

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised February 7, 2018

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