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S29WS128N0SBFW013

Description
存储器 IC
Categorysemiconductor    memory   
File Size2MB,79 Pages
ManufacturerCypress Semiconductor
Environmental Compliance
Download Datasheet Parametric View All

S29WS128N0SBFW013 Overview

存储器 IC

S29WS128N0SBFW013 Parametric

Parameter NameAttribute value
category
MakerCypress Semiconductor
series-
PackageBulk
S29WS256N
S29WS128N
256/128 Mbit (16/8 M x 16 bit), 1.8 V,
Simultaneous Read/Write, Burst Flash
This product family has been retired and is not recommended for designs. For new and current designs, the S29WS128P and
S29WS256P supersede the S29WS128N and S29WS256N respectively. These are the factory-recommended migration paths.
Please refer to the S29WS-P Family data sheet for specifications and ordering information.
General Description
The Spansion S29WS256/128 are Mirrorbit
TM
Flash products fabricated on 110 nm process technology. These burst mode Flash
devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate
data and address pins. These products can operate up to 80 MHz and use a single V
CC
of 1.7 V to 1.95 V that makes them ideal for
today’s demanding wireless applications requiring higher density, better performance and lowered power consumption.
Distinctive Characteristics
110 nm MirrorBit™ Technology
Dual boot sector configuration (top and bottom)
Offered Packages
WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
Low V
CC
write inhibit
Persistent and Password methods of Advanced Sector Protection
Write operation status bits indicate program and erase operation
completion
Suspend and Resume commands for Program and Erase
operations
Simultaneous Read/Write operation with zero latency
32-word Write Buffer
Sixteen-bank architecture consisting of 16/8 Mwords for WS256N/
128N, respectively
Four 16 Kword sectors at both top and bottom of memory array
254/126 64 Kword sectors (WS256N/128N)
Programmable linear (8/16/32) with or without wrap around and
continuous burst read modes
Secured Silicon Sector region consisting of 128 words each for
factory and customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector (typical)
RDY output indicates data available to system
Command set compatible with JEDEC (42.4) standard
Read Access Times
Speed Option (MHz)
Max. Synch. Latency, ns (t
IACC
)
Max. Synch. Burst Access, ns (t
BACC
)
Max. Asynch. Access Time, ns (t
ACC
)
om
Performance Characteristics
80
m
en
de
d
fo
Unlock Bypass program command to reduce programming time
Synchronous or Asynchronous program operation, independent of
burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
rN
ec
66
80
54
80
13.5
80
20
80
13.5
Continuous Burst Read @ 80 MHz
Simultaneous Operation (asynchronous)
Program (asynchronous)
Erase (asynchronous)
Standby Mode (asynchronous)
ew
Current Consumption (typical values)
38 mA
50 mA
19 mA
19 mA
20 µA
R
80
9
11.2
80
20
80
13.5
ot
80
20
80
13.5
Max. Asynch. Page Access Time, ns (t
PACC
)
Max CE# Access Time, ns (t
CE
)
Max OE# Access Time, ns (t
OE
)
N
Single Word Programming
Effective Write Buffer Programming (V
CC
) Per Word
Effective Write Buffer Programming (V
ACC
) Per Word
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
D
Typical Program & Erase Times
40 µs
9.4 µs
6 µs
150 ms
600 ms
Cypress Semiconductor Corporation
Document Number: 002-01825 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised January 08, 2016
es
ig
n
Single 1.8 V read/program/erase (1.70–1.95 V)
Hardware (WP#) protection of top and bottom sectors
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