S34ML08G201TFB000 datasheet, PDF

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S34ML08G1

8 Gb, 1-bit ECC, x8 I/O, 3 V, V

CC

NAND Flash Memory for Embedded

General Description

The Cypress S34ML08G1 8-Gb NAND is offered in 3.3 V

CC

with x8 I/O interface. This document contains information for the

S34ML08G1 device, which is a dual-die stack of two S34ML04G1 die. For detailed specifications, please refer to the discrete die

datasheet:

S34ML04G1.

Distinctive Characteristics



Density

– 8 Gb (4 Gb



2)



Architecture (For each 4 Gb device)

– Input / Output Bus Width: 8-bits

– Page Size: (2048 + 64) bytes; 64 bytes is spare area

– Block Size: 64 Pages or (128k + 4k) bytes

– Plane Size

– 2048 Blocks per Plane or (256M + 8M) bytes

– Device Size

– 2 Planes per Device or 512 Mbyte



NAND Flash Interface

– Open NAND Flash Interface (ONFI) 1.0 compliant

– Address, Data and Commands multiplexed



Supply Voltage

– 3.3 V device: Vcc = 2.7 V ~ 3.6 V



Security

– One Time Programmable (OTP) area

– Hardware program/erase disabled during power transition



Additional Features

– Supports Multiplane Program and Erase commands

– Supports Copy Back Program

– Supports Multiplane Copy Back Program

– Supports Read Cache



Electronic Signature

– Manufacturer ID: 01h



Operating Temperature

– Industrial:

40

°C to 85 °C

– Automotive:

40

°C to 105 °C

Performance



Page Read / Program

– Random access: 25 µs (Max)

– Sequential access: 25 ns (Min)

– Program time / Multiplane Program time: 200 µs (Typ)



Block Erase / Multiplane Erase (S34ML04G1)

– Block Erase time: 3.5 ms (Typ)



Reliability

– 100,000 Program / Erase cycles (Typ)

(with 1 bit / 512 + 16 byte ECC)

– 10 Year Data retention (Typ)

– Blocks zero and one are valid and will be valid for at least

1000 program-erase cycles with ECC



Package Options

– Lead Free and Low Halogen

– 48-Pin TSOP 12



20



1.2 mm

– 63-Ball BGA 9



11



1 mm

Cypress Semiconductor Corporation

Document Number: 002-00483 Rev. *H

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Revised January 12, 2016

S34ML08G1

Contents

1.

2.

3.

4.

5.

6.

7.

7.1

Connection Diagram....................................................

3

Pin Description.............................................................

5

Block Diagrams............................................................

6

Addressing

................................................................... 8

Read Status Enhanced

................................................ 9

Extended Read Status

................................................. 9

Read ID........................................................................

10

Read Parameter Page ................................................. 11

8.

8.1

8.2

8.3

8.4

9.

9.1

10.

11.

12.

Electrical Characteristics

........................................... 13

Valid Blocks .................................................................. 13

DC Characteristics ........................................................ 14

Pin Capacitance............................................................ 14

Power Consumptions and Pin Capacitance for Allowed

Stacking Configurations ................................................ 14

Physical Interface

....................................................... 15

Physical Diagram .......................................................... 15

Ordering Information

.................................................. 17

Appendix A — Errata

.................................................. 18

Revision History..........................................................

19

Document Number: 002-00483 Rev. *H

Page 2 of 21

S34ML08G1

1. Connection Diagram

Figure 1.1

48-Pin TSOP1 Contact x8 Device (1 CE 8 Gb)

NC

R/B#

RE#

CE#

NC

VCC

VSS

NC

CLE

ALE

WE#

WP#

NC

1

48

12

13

NAND Flash

TSOP1

(x8)

37

36

VSS

(1)

NC

I/O7

I/O6

I/O5

I/O4

NC

(1)

VCC

NC

VCC

VSS

NC

VCC

(1)

NC

I/O3

I/O2

I/O1

I/O0

NC

VSS

(1)

24

25

Note:

1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.

Figure 1.2

48-Pin TSOP1 Contact x8 Device (2 CE 8 Gb)

NC

R/B2#

R/B1#

RE#

CE1#

CE2#

NC

VCC

VSS

NC

CLE

ALE

WE#

WP#

NC

1

48

12

13

NAND Flash

TSOP1

(x8)

37

36

24

25

VSS

(1)

NC

I/O7

I/O6

I/O5

I/O4

NC

VCC

(1)

NC

VCC

VSS

NC

VCC

(1)

NC

I/O3

I/O2

I/O1

I/O0

NC

VSS

(1)

Note:

1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.

Document Number: 002-00483 Rev. *H

Page 3 of 21

S34ML08G1

Figure 1.3

63-BGA Contact, x8 Device, Single CE (Top View)

A1

NC

B1

NC

A2

NC

A9

NC

B9

NC

C3

WP#

D3

VCC

(1)

E3

NC

F3

NC

G3

NC

H3

NC

J3

NC

K3

V

SS

C4

ALE

D4

RE#

E4

NC

F4

NC

G4

VCC

(1)

H4

I/O0

J4

I/O1

K4

I/O2

C5

VSS

D5

CLE

E5

NC

F5

NC

G5

NC

H5

NC

J5

NC

K5

I/O3

C6

CE#

D6

NC

E6

NC

F6

NC

G6

NC

H6

NC

J6

V

CC

K6

I/O4

C7

WE#

D7

NC

E7

NC

F7

VSS

(1)

G7

NC

H7

NC

J7

I/O5

K7

I/O6

C8

RB#

D8

NC

E8

NC

F8

NC

G8

NC

H8

V

cc

J8

I/O7

K8

V

SS

L9

NC

M9

NC

A10

NC

B10

NC

L1

NC

M1

NC

L2

NC

M2

NC

L10

NC

M10

NC

Note:

1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.

Document Number: 002-00483 Rev. *H

Page 4 of 21

S34ML08G1

2.

Pin Description

Table 2.1

Pin Description

Pin Name

I/O0 - I/O7

CLE

ALE

CE#

WE#

RE#

WP#

R/B#

VCC

VSS

NC

Description

Inputs/Outputs.

The I/O pins are used for command input, address input, data input, and data output. The

I/O pins float to High-Z when the device is deselected or the outputs are disabled.

Command Latch Enable.

This input activates the latching of the I/O inputs inside the Command Register on the rising

edge of Write Enable (WE#).

Address Latch Enable.

This input activates the latching of the I/O inputs inside the Address Register on the rising

edge of Write Enable (WE#).

Chip Enable.

This input controls the selection of the device. When the device is not busy CE# low selects the memory.

Write Enable.

This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#.

Read Enable.

The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is

valid t

REA

after the falling edge of RE# which also increments the internal column address counter by one.

Write Protect.

The WP# pin, when low, provides hardware protection against undesired data modification

(program / erase).

Ready Busy.

The Ready/Busy output is an Open Drain pin that signals the state of the memory.

Supply Voltage.

The V

CC

supplies the power for all the operations (Read, Program, Erase). An internal lock circuit

prevents the insertion of Commands when V

CC

is less than V

LKO

.

Ground.

Not Connected.

Notes:

1. A 0.1 µF capacitor should be connected between the V

CC

Supply Voltage pin and the V

SS

Ground pin to decouple the current surges from the power supply. The PCB

track widths must be sufficient to carry the currents required during program and erase operations.

2. An internal voltage detector disables all functions whenever V

CC

is below 1.8V to protect the device from any involuntary program/erase during power transitions.

Document Number: 002-00483 Rev. *H

Page 5 of 21

Parameter Name	Attribute value
category
Maker	Cypress Semiconductor
series	Automotive, AEC-Q100, ML-2
Package	tray
memory type	non-volatile
memory format	flash memory
technology	闪存 - NAND
storage	8Gb
memory organization	1G x 8
memory interface	in parallel
Write cycle time - words, pages	25ns
Voltage - Power supply	2.7V ~ 3.6V
Operating temperature	-40°C ~ 105°C（TA）
Installation type	surface mount type
Package/casing	48-TFSOP (0.724", 18.40mm wide)
Supplier device packaging	48-TSOP I
Basic product number	S34ML08

S34ML08G201TFB000

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