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S29AS016J
16 Mbit (2 M x 8-Bit/1 M x 16-Bit), 1.8 V
Boot Sector Flash
Distinctive Characteristics
Architectural Advantages
■
Package Options
■
■
■
Single Power Supply Operation
❐
Full voltage range: 1.65 to 1.95 volt read and write operations
for battery-powered applications
Manufactured on 110 nm Process Technology
❐
Backward compatible with 0.32 µm Am29SL160C device
Secured Silicon Sector region
❐
128-word/256-byte sector for permanent, secure identifica-
tion through an 8-word/16-byte random Electronic Serial
Number, accessible through a command sequence
❐
May be programmed and locked at the factory or by the
customer
Flexible Sector Architecture
❐
Eight 8 Kbyte and thirty-one 64 Kbyte sectors (byte mode)
❐
Eight 4 Kword, and thirty-one 32 Kword sectors (word mode)
Sector Group Protection Features
❐
A hardware method of locking a sector to prevent any program
or erase operations within that sector
❐
Sectors can be locked in-system or via programming equip-
ment
❐
Temporary Sector Group Unprotect feature allows code
changes in previously locked sectors
Unlock Bypass Program Command
❐
Reduces overall programming time when issuing multiple
program command sequences
Top or Bottom Boot Block Configurations Available
Compatibility with JEDEC standards
❐
Pinout and software compatible with single-power supply
Flash
❐
Superior inadvertent write protection
48-ball Fine-Pitch BGA, 8.15 mm x 6.15 mm
48-ball Fine-Pitch BGA, 6.0 mm x 4.0 mm
48-pin TSOP
■
Software Features
■
■
CFI (Common Flash Interface) Compliant
❐
Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
Erase Suspend/Erase Resume
❐
Suspends an erase operation to read data from, or program
data to, a sector that is not being erased, then resumes the
erase operation
Data# Polling and Toggle Bits
❐
Provides a software method of detecting program or erase
operation completion
■
■
■
■
Hardware Features
■
Ready/Busy# Pin (RY/BY#)
❐
Provides a hardware method of detecting program or erase
cycle completion
Hardware Reset Pin (RESET#)
❐
Hardware method to reset the device to reading array data
WP# Input Pin
❐
Write protect (WP#) function allows protection of two outer-
most boot sectors (boot sector models only), regardless of
sector group protect status
■
■
■
■
■
Performance Characteristics
■
High Performance
❐
Access times as fast as 70 ns
❐
Industrial temperature range (-40 °C to +85 °C)
❐
Industrial Plus temperature range (-40 °C to +105 °C)
❐
Automotive, AEC-Q100 Grade 3 (-40 °C to +85 °C)
❐
Automotive, AEC-Q100 Grade 2 (-40 °C to +105 °C)
❐
Word programming time as fast as 6 µs (typical)
Ultra Low Power Consumption (typical values at 5 MHz)
❐
15 µA Automatic Sleep mode current
❐
8 µA standby mode current
❐
8 mA read current
❐
20 mA program/erase current
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
■
■
■
Cypress Semiconductor Corporation
Document Number: 002-01122 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 16, 2019
S29AS016J
General Description
The S29AS016J is a 16 Mbit, 1.8 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words with a x8/x16 bus and
either top or bottom boot sector architecture. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word-wide data
(x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and
erased in-system with the standard system 1.8 volt V
CC
supply. A 12.0V V
PP
or 5.0 V
CC
are not required for program or erase
operations. The device can also be programmed in standard EPROM programmers.
The device offers access time of 70 ns allowing high speed microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a
single 1.8 volt power supply
for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The S29AS016J is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine
that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the
Embedded Program
algorithm—an
internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass
mode
facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the
Embedded Erase
algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During
erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7
(Data# Polling) and DQ6 (toggle)
status bits.
After a program or erase cycle has been completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during power
transitions. The
hardware sector group protection
feature disables both program and erase operations in any combination of the
sectors of memory. This can be achieved in-system or via programming equipment.
The
Erase Suspend/Erase Resume
feature enables the user to put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to reading array data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters
the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly reduced in
both these modes.
Cypress Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim
tunneling. The data is programmed using hot electron injection.
Document Number: 002-01122 Rev. *M
Page 2 of 57
S29AS016J
Contents
1.
2.
3.
3.1
3.2
3.3
3.4
4.
5.
6.
6.1
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
8.
8.1
8.2
9.
10.
10.1
10.2
10.3
10.4
Product Selector Guide
............................................... 4
Block Diagram..............................................................
4
Connection Diagrams..................................................
5
Standard TSOP.............................................................. 5
FBGA Connection Diagram, 8.15 mm x 6.15 mm
(VBK048) ....................................................................... 6
FBGA Connection Diagram, 6.0 mm x 4.0 mm
(VDF048) ....................................................................... 7
Special Handling Instructions......................................... 7
Pin Configuration.........................................................
8
Logic Symbol
............................................................... 8
Ordering Information
................................................... 9
S29AS016J Standard Products ..................................... 9
Device Bus Operations..............................................
Word/Byte Configuration..............................................
Requirements for Reading Array Data.........................
Writing Commands/Command Sequences..................
Program and Erase Operation Status..........................
Standby Mode..............................................................
Automatic Sleep Mode.................................................
RESET#: Hardware Reset Pin.....................................
Output Disable Mode ...................................................
Autoselect Mode ..........................................................
Sector Address Tables.................................................
Sector Group Protection/Unprotection .........................
Temporary Sector Group Unprotect.............................
Write Protect (WP#) .....................................................
Hardware Data Protection............................................
11
12
12
12
12
13
13
13
13
14
15
17
20
20
20
10.5
10.6
10.7
10.8
10.9
11.
12.
12.1
12.2
12.3
12.4
12.5
12.6
12.7
13.
14.
Word/Byte Program Command Sequence.................... 28
Unlock Bypass Command Sequence ........................... 28
Chip Erase Command Sequence ................................. 29
Sector Erase Command Sequence .............................. 30
Erase Suspend/Erase Resume Commands ................. 30
Command Definitions.................................................
32
Write Operation Status
............................................... 34
DQ7: Data# Polling ....................................................... 34
RY/BY#: Ready/Busy#.................................................. 35
DQ6: Toggle Bit I .......................................................... 36
DQ2: Toggle Bit II ......................................................... 36
Reading Toggle Bits DQ6/DQ2..................................... 36
DQ5: Exceeded Timing Limits ...................................... 37
DQ3: Sector Erase Timer.............................................. 38
Absolute Maximum Ratings.......................................
39
Operating Ranges
....................................................... 39
15. DC Characteristics......................................................
40
15.1 CMOS Compatible ........................................................ 40
16.
17.
18.
18.1
18.2
18.3
18.4
18.5
18.6
19.
20.
21.
Test Conditions
........................................................... 41
Key to Switching Waveforms.....................................
41
AC Characteristics......................................................
42
Read Operations........................................................... 42
Hardware Reset (RESET#)........................................... 43
Word/Byte Configuration (BYTE#) ................................ 44
Erase/Program Operations ........................................... 45
Temporary Sector Group Unprotect.............................. 48
Alternate CE# Controlled Erase/Program
Operations ....................................................................49
Erase and Programming Performance
..................... 51
Package Pin Capacitance...........................................
51
Physical Dimensions
.................................................. 52
Secured Silicon Sector Flash Memory Region
....... 22
Factory Locked: Secired Silicon Sector
Programmed and Protected at the Factory .................. 22
Customer Lockable: Secured Silicon Sector
NOT Programmed or Protected at the Factory ............ 22
Common Flash Memory Interface (CFI)
................... 24
Command Definitions................................................
27
Reading Array Data ..................................................... 27
Reset Command .......................................................... 27
Autoselect Command Sequence ................................. 27
Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence ........................................ 28
22. Document History
....................................................... 55
Sales, Solutions, and Legal Information .......................... 57
Worldwide Sales and Design Support ...........................57
Products ........................................................................57
PSoC® Solutions ..........................................................57
Cypress Developer Community .....................................57
Technical Support .........................................................57
Document Number: 002-01122 Rev. *M
Page 3 of 57
S29AS016J
1.
Product Selector Guide
Family Part Number
Speed Option
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max OE# access time, ns (t
OE
)
Note
1. See
Section 18. AC Characteristics on page 42
for full specifications.
S29AS016J
70
70
70
25
Voltage Range: V
CC
= 1.65–1.95 V
2. Block Diagram
RY/BY#
V
CC
V
SS
RESET#
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
DQ0
–
DQ15 (A-1)
WE#
BYTE#
WP#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data
Latch
CE#
OE#
Y-Decoder
Y-Gating
V
CC
Detector
Timer
Address Latch
X-Decoder
Cell Matrix
A0–A19
Document Number: 002-01122 Rev. *M
Page 4 of 57
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