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74LVCH16245ADGVJ

Description
收发器,非反相 2 元件 8 位每元件 三态 Output 48-TSSOP
Categorylogic    Logic - buffer, drives, receiver, transceiver   
File Size256KB,15 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
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74LVCH16245ADGVJ Overview

收发器,非反相 2 元件 8 位每元件 三态 Output 48-TSSOP

74LVCH16245ADGVJ Parametric

Parameter NameAttribute value
category
MakerNexperia
series74LVCH
Package卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带
logical typetransceiver, non-inverting
Number of components2
Number of digits per component8
input type-
Output typeThree states
Current - Output High, Low24mA,24mA
Voltage - Power supply1.2V ~ 3.6V
Operating temperature-40°C ~ 125°C(TA)
Installation typesurface mount type
Package/casing48-TFSOP (0.173", 4.40mm wide)
Supplier device packaging48-TSSOP
Basic product number74LVCH16245
74LVC16245A; 74LVCH16245A
Rev. 14 — 24 September 2021
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
Product data sheet
1. General description
The 74LVC16245A; 74LVCH16245A is a 16-bit transceiver with 3-state outputs. The device can be
used as two 8-bit transceivers or one 16-bit transceiver. The device features two output enables
(1OE and 2OE) each controlling eight outputs, and two send/receive (1DIR and 2DIR) inputs for
direction control. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
The 74LVCH16245A bus hold on data inputs eliminates the need for external pull-up resistors to
hold unused inputs.
2. Features and benefits
Overvoltage tolerant inputs to 5.5 V
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power dissipation
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground bounce
Direct interface with TTL levels
I
OFF
circuitry provides partial Power-down mode operation
All data inputs have bus hold (74LVCH16245A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C

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