256Mb: x16, x32 Mobile LPDDR SDRAM
Features
Mobile Low-Power DDR SDRAM
MT46H16M16LF – 4 Meg x 16 x 4 Banks
MT46H8M32LF – 2 Meg x 32 x 4 Banks
Features
•
V
DD
/V
DDQ
= 1.70–1.95V
•
Bidirectional data strobe per byte of data (DQS)
•
Internal, pipelined double data rate (DDR) architec-
ture; two data accesses per clock cycle
•
Differential clock inputs (CK and CK#)
•
Commands entered on each positive CK edge
•
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
•
4 internal banks for concurrent operation
•
Data masks (DM) for masking write data—one mask
per byte
•
Programmable burst lengths (BL): 2, 4, 8, or 16
•
Concurrent auto precharge option is supported
•
Auto refresh and self refresh modes
•
1.8V LVCMOS-compatible inputs
•
On-chip temp sensor to control self refresh rate
•
Partial-array self refresh (PASR)
•
Deep power-down (DPD)
•
Status read register (SRR)
•
Selectable output drive strength (DS)
•
Clock stop capability
•
64ms refresh
Options
•
V
DD
/V
DDQ
–
1.8V/1.8V
•
Configuration
–
16 Meg x 16 (4 Meg x 16 x 4 banks)
–
8 Meg x 32 (2 Meg x 32 x 4 banks)
•
Row-size option
–
JEDEC-standard option
–
Reduced page-size option
2
•
Plastic "green" package
–
60-ball VFBGA (8mm x 9mm)
1
–
90-ball VFBGA (8mm x 13mm)
2
•
Timing – cycle time
–
5ns @ CL = 3 (200 MHz)
–
5.4ns @ CL = 3 (185 MHz)
–
6ns @ CL = 3 (166 MHz)
–
7.5ns @ CL = 3 (133 MHz)
•
Operating temperature range
–
Commercial (0˚ to +70˚C)
–
Industrial (–40˚C to +85˚C)
•
Design revision
Notes:
Marking
H
16M16
8M32
LF
LG
BF
B5
-5
-54
-6
-75
None
IT
:H
1. Only available for x16 configuration.
2. Only available for x32 configuration.
Table 1: Configuration Addressing
Reduced
Page-Size
Option
2
2 Meg x 32
x 4 banks
8K
8K A[12:0]
256 A[7:0]
Architecture 16 Meg x 16 8 Meg x 32
Configuration 4 Meg x 16 x 2 Meg x 32 x
4 banks
4 banks
Refresh count
Row
addressing
Column
addressing
8K
8K A[12:0]
512 A[8:0]
4K
4K A[11:0]
512 A[8:0]
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile LPDDR SDRAM
Features
Figure 1: 256Mb Mobile LPDDR Part Numbering
MT 46
Micron Technology
Product family
46 = Mobile DDR SDRAM
H
16M16 LF BF
-6
IT
:H
Revision
:H
Operating temperature
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Operating voltage
H = 1.8V/1.8V
Cycle time
Configuration
16 Meg x 16
8 Meg x 32
-5 = 5ns
t
CK, CL = 3
-54 = 5.4ns
t
CK, CL = 3
-6 = 6ns
t
CK, CL = 3
-75 = 7.5ns
t
CK, CL = 3
Addressing
LF = Mobile standard addressing
LG = Reduced page-size addressing
Package codes
BF = 8mm x 9mm VFBGA “green”
B5 = 8mm x 13mm VFBGA “green”
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at
www.micron.com/decoder.
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile LPDDR SDRAM
Features
General Description ......................................................................................................................................... 8
Functional Block Diagrams ............................................................................................................................... 9
Ball Assignments and Descriptions ................................................................................................................. 11
Package Dimensions ...................................................................................................................................... 15
Electrical Specifications .................................................................................................................................. 17
Electrical Specifications – I
DD
Parameters ........................................................................................................ 20
Electrical Specifications – AC Operating Conditions ......................................................................................... 24
Output Drive Characteristics ........................................................................................................................... 29
Functional Description ................................................................................................................................... 32
Commands .................................................................................................................................................... 33
DESELECT ................................................................................................................................................ 34
NO OPERATION ........................................................................................................................................ 34
LOAD MODE REGISTER ............................................................................................................................ 34
ACTIVE ..................................................................................................................................................... 34
READ ........................................................................................................................................................ 35
WRITE ...................................................................................................................................................... 36
PRECHARGE ............................................................................................................................................. 37
BURST TERMINATE .................................................................................................................................. 38
AUTO REFRESH ........................................................................................................................................ 38
SELF REFRESH ........................................................................................................................................... 39
DEEP POWER-DOWN ................................................................................................................................ 39
Truth Tables ................................................................................................................................................... 40
State Diagram ................................................................................................................................................ 45
Initialization .................................................................................................................................................. 46
Standard Mode Register .................................................................................................................................. 49
Burst Length .............................................................................................................................................. 49
Burst Type ................................................................................................................................................. 50
CAS Latency .............................................................................................................................................. 51
Operating Mode ......................................................................................................................................... 52
Extended Mode Register ................................................................................................................................. 53
Temperature-Compensated Self Refresh .................................................................................................... 53
Partial-Array Self Refresh ........................................................................................................................... 54
Output Drive Strength ................................................................................................................................ 54
Status Read Register ....................................................................................................................................... 55
Bank/Row Activation ...................................................................................................................................... 57
READ Operation ............................................................................................................................................. 58
WRITE Operation ........................................................................................................................................... 69
PRECHARGE Operation .................................................................................................................................. 81
Auto Precharge ............................................................................................................................................... 81
Concurrent Auto Precharge ........................................................................................................................ 82
AUTO REFRESH Operation ............................................................................................................................. 87
SELF REFRESH Operation .............................................................................................................................. 88
Power-Down .................................................................................................................................................. 89
Deep Power-Down .................................................................................................................................... 91
Clock Change Frequency ................................................................................................................................ 93
Revision History ............................................................................................................................................. 94
Rev. I, Production – 09/10 ........................................................................................................................... 94
Rev. H, Production – 11/09 .......................................................................................................................... 94
Rev. G, Production – 09/09 .......................................................................................................................... 94
Rev. F, Production – 4/09 ............................................................................................................................ 94
Contents
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile LPDDR SDRAM
Features
Rev. E, Production – 3/09 ............................................................................................................................
Rev. D, Production – 02/09 ..........................................................................................................................
Rev. C, Production – 01/09 ..........................................................................................................................
Rev. B, Preliminary – 10/08 .........................................................................................................................
Rev. A, Advance – 08/08 ..............................................................................................................................
Revision History for Commands, Operations, and Timing Diagrams .............................................................
Update – 01/09 ...........................................................................................................................................
Update – 07/08 ...........................................................................................................................................
Update – 05/08 ...........................................................................................................................................
Update – 03/08 ...........................................................................................................................................
Update – 12/07 ...........................................................................................................................................
Update – 07/07 ...........................................................................................................................................
94
94
94
94
95
95
95
95
95
95
96
96
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile LPDDR SDRAM
Features
Figure 1: 256Mb Mobile LPDDR Part Numbering ............................................................................................. 2
Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10
Figure 4: 60-Ball VFBGA – 8mm x 9mm (Top View) ......................................................................................... 11
Figure 5: 90-Ball VFBGA – 8mm x 13mm (Top View) ....................................................................................... 12
Figure 6: 60-Ball VFBGA (8mm x 9mm) .......................................................................................................... 15
Figure 7: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 16
Figure 8: Typical Self Refresh Current vs. Temperature ................................................................................... 23
Figure 9: ACTIVE Command .......................................................................................................................... 35
Figure 10: READ Command ........................................................................................................................... 36
Figure 11: WRITE Command ......................................................................................................................... 37
Figure 12: PRECHARGE Command ................................................................................................................ 38
Figure 13: DEEP POWER-DOWN Command .................................................................................................. 39
Figure 14: Simplified State Diagram ............................................................................................................... 45
Figure 15: Initialize and Load Mode Registers ................................................................................................. 47
Figure 16: Alternate Initialization with CKE LOW ............................................................................................ 48
Figure 17: Standard Mode Register Definition ................................................................................................ 49
Figure 18: CAS Latency .................................................................................................................................. 52
Figure 19: Extended Mode Register ................................................................................................................ 53
Figure 20: Status Read Register Timing .......................................................................................................... 55
Figure 21: Status Register Definition .............................................................................................................. 56
Figure 22: READ Burst ................................................................................................................................... 59
Figure 23: Consecutive READ Bursts .............................................................................................................. 60
Figure 24: Nonconsecutive READ Bursts ........................................................................................................ 61
Figure 25: Random Read Accesses ................................................................................................................. 62
Figure 26: Terminating a READ Burst ............................................................................................................. 63
Figure 27: READ-to-WRITE ............................................................................................................................ 64
Figure 28: READ-to-PRECHARGE .................................................................................................................. 65
Figure 29: Data Output Timing –
t
DQSQ,
t
QH, and Data Valid Window (x16) ................................................... 66
Figure 30: Data Output Timing –
t
DQSQ,
t
QH, and Data Valid Window (x32) ................................................... 67
Figure 31: Data Output Timing –
t
AC and
t
DQSCK .......................................................................................... 68
Figure 32: Data Input Timing ......................................................................................................................... 70
Figure 33: Write – DM Operation ................................................................................................................... 71
Figure 34: WRITE Burst ................................................................................................................................. 72
Figure 35: Consecutive WRITE-to-WRITE ....................................................................................................... 73
Figure 36: Nonconsecutive WRITE-to-WRITE ................................................................................................. 73
Figure 37: Random WRITE Cycles .................................................................................................................. 74
Figure 38: WRITE-to-READ – Uninterrupting ................................................................................................. 75
Figure 39: WRITE-to-READ – Interrupting ...................................................................................................... 76
Figure 40: WRITE-to-READ – Odd Number of Data, Interrupting .................................................................... 77
Figure 41: WRITE-to-PRECHARGE – Uninterrupting ...................................................................................... 78
Figure 42: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 79
Figure 43: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting ......................................................... 80
Figure 44: Bank Read – With Auto Precharge .................................................................................................. 83
Figure 45: Bank Read – Without Auto Precharge ............................................................................................. 84
Figure 46: Bank Write – With Auto Precharge .................................................................................................. 85
Figure 47: Bank Write – Without Auto Precharge ............................................................................................. 86
Figure 48: Auto Refresh Mode ........................................................................................................................ 87
Figure 49: Self Refresh Mode ......................................................................................................................... 89
Figure 50: Power-Down Entry (in Active or Precharge Mode) .......................................................................... 90
List of Figures
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
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