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MT41K512M8DA-107 IT:P TR

Description
SDRAM - DDR3L 存储器 IC 4Gb(512M x 8) 并联 933 MHz 20 ns 78-FBGA(8x10.5)
Categorysemiconductor    memory   
File Size5MB,214 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT41K512M8DA-107 IT:P TR Overview

SDRAM - DDR3L 存储器 IC 4Gb(512M x 8) 并联 933 MHz 20 ns 78-FBGA(8x10.5)

MT41K512M8DA-107 IT:P TR Parametric

Parameter NameAttribute value
category
MakerMicron Technology
series-
PackageTape and Reel (TR)
memory typeVolatile
memory formatDRAM
technologySDRAM - DDR3L
storage4Gb(512M x 8)
memory interfacein parallel
Write cycle time - words, pages15ns
Voltage - Power supply1.283V ~ 1.45V
Operating temperature-40°C ~ 95°C(TC)
Installation typesurface mount type
Package/casing78-TFBGA
Supplier device packaging78-FBGA(8x10.5)
Clock frequency933 MHz
interview time20 ns
Basic product numberMT41K512M8
4Gb: x8, x16 Automotive DDR3L SDRAM
Description
Automotive DDR3L SDRAM
MT41K512M8 – 64 Meg x 8 x 8 banks
MT41K256M16 – 32 Meg x 16 x 8 banks
Description
DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM (Die
Rev :E) data sheet specifications when running in 1.5V
compatible mode.
Features
Options
Marking
512M8
256M16
V
DD
= V
DDQ
= 1.35V (1.283–1.45V)
Backward compatible to V
DD
= V
DDQ
= 1.5V
±0.075V
Supports DDR3L devices to be backward compati-
ble in 1.5V applications
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable posted CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
T
C
of -40°C to +125°C
64ms, 8192-cycle refresh at -40°C to +85°C
32ms at +85°C to +105°C
16ms at +105°C to +115°C
8ms at +115°C to +125°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Write leveling
Multipurpose register
Output driver calibration
AEC-Q100
Configuration
512 Meg x 8
256 Meg x 16
• FBGA package (Pb-free) –
x8
78-ball
(8mm
x
10.5mm)
• FBGA package (Pb-free) –
x16
96-ball (8mm x 14mm)
• Timing – cycle time
1.07ns @ CL = 13
(DDR3-1866)
Automotive grade
AEC-Q100
PPAP submission
Operating temperature
– Industrial (–40°C
T
C
+95°C)
– Automotive (–40°C
T
C
+105°C)
– Ultra-high (–40°C
T
C
+125°C)
3
Revision
DA
TW
-107
A
IT
AT
UT
:P
Notes: 1. Not all options listed can be combined to define
an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
2. The data sheet does not support
×4
mode even
though
×4
mode description exists in the
following sections.
3. The UT option use based on automotive usage
model. Please contact Micron sales representative
if you have questions.
CCMTD-1725822587-10208
automotive_4gb_ddr3l_v00h.pdf - Rev. I 09/2021 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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