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MT46H32M32LFCG-6:A TR

Description
SDRAM - 移动 LPDDR 存储器 IC 1Gb(32M x 32) 并联 166 MHz 5 ns 152-VFBGA(14x14)
Categorysemiconductor    memory   
File Size274KB,12 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT46H32M32LFCG-6:A TR Overview

SDRAM - 移动 LPDDR 存储器 IC 1Gb(32M x 32) 并联 166 MHz 5 ns 152-VFBGA(14x14)

MT46H32M32LFCG-6:A TR Parametric

Parameter NameAttribute value
category
MakerMicron Technology
series-
PackageTape and Reel (TR)
memory typeVolatile
memory formatDRAM
technologySDRAM - Mobile LPDDR
storage1Gb(32M x 32)
memory interfacein parallel
Write cycle time - words, pages15ns
Voltage - Power supply1.7V ~ 1.95V
Operating temperature0°C ~ 70°C(TA)
Installation typesurface mount type
Package/casing152-VFBGA
Supplier device packaging152-VFBGA(14x14)
Clock frequency166 MHz
interview time5 ns
Basic product numberMT46H32M32
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Features
Mobile LPDDR (only)
152-Ball Package-on-Package (PoP) TI-OMAP™
MT46HxxxMxxLxCG
MT46HxxxMxxLxKZ
Features
• V
DD/
V
DDQ
= 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; 2 data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data—one mask
per byte
• Programmable burst lengths (BLs): 2, 4, 8, or 16
1
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• STATUS REGISTER READ (SRR) supported
2
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh
Options
Marking
• V
DD/
V
DDQ
1.8V/1.8V
H
• Configuration
128 Meg x 32 (16 Meg x 16 x 4 banks x 4) 128M32
64M32
64 Meg x 32 (8 Meg x 32 x 4 banks x 2)
32M32
32 Meg x 32 (8 Meg x 32 x 4 banks)
16M32
16 Meg x 32 (4 Meg x 32 x 4 banks)
• Device version
Single die, standard addressing
LF
2-die stack, standard addressing
L2
4-die stack, standard addressing
L4
• Plastic “green” package
152-ball VFBGA (14 x 14 x 1.0mm)
CG
152-ball VFBGA (14 x 14 x 1.2mm)
KZ
• Timing – cycle time
5ns @ CL = 3
-5
5.4ns @ CL = 3
-54
-6
6ns @ CL = 3
• Operating temperature range
Commercial (0°C to +70°C)
None
Industrial (–40°C to +85°C)
IT
Notes: 1. BL 16: contact factory for availability.
2. Contact factory for remapped SRR output.
Table 1:
Architecture
Configuration
Configuration Addressing
128 Meg x 32
1
16 Meg x 16
x 4 banks x 4 die
8K
16K (A[13:0])
1K (A[9:0])
Notes:
64 Meg x 32
8 Meg x 32
x 4 banks x 2 die
8K
8K (A[12:0])
1K (A[9:0])
32 Meg x 32
8 Meg x 32
x 4 banks
8K
8K (A[12:0])
1K (A[9:0])
16 Meg x 32
4 Meg x 32
x 4 banks
8K
8K (A[12:0])
512 (A[8:0])
Refresh count
Row addressing
Column addressing
1. Quad die stack. Each CS configured with two x16 die connected in parallel to make up a 32-bit-
wide bus.
PDF: 09005aef833913f1/Source: 09005aef833913d6
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
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