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MT48LC32M16A2TG-75 IT:C TR

Description
SDRAM 存储器 IC 512Mb(32M x 16) 并联 133 MHz 5.4 ns 54-TSOP II
Categorysemiconductor    memory   
File Size1MB,77 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT48LC32M16A2TG-75 IT:C TR Overview

SDRAM 存储器 IC 512Mb(32M x 16) 并联 133 MHz 5.4 ns 54-TSOP II

MT48LC32M16A2TG-75 IT:C TR Parametric

Parameter NameAttribute value
category
MakerMicron Technology
series-
Package卷带(TR)剪切带(CT)Digi-Reel®
memory typeVolatile
memory formatDRAM
technologySDRAM
storage512Mb(32M x 16)
memory interfacein parallel
Write cycle time - words, pages15ns
Voltage - Power supply3V ~ 3.6V
Operating temperature-40°C ~ 85°C(TA)
Installation typesurface mount type
Package/casing54-TSOP (0.400", 10.16mm wide)
Supplier device packaging54-TSOP II
Clock frequency133 MHz
interview time5.4 ns
Basic product numberMT48LC32M16A2
512Mb: x4, x8, x16 SDRAM
Features
SDR SDRAM
MT48LC128M4A2 – 32 Meg x 4 x 4 banks
MT48LC64M8A2 – 16 Meg x 8 x 4 banks
MT48LC32M16A2 – 8 Meg x 16 x 4 banks
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode
• Auto refresh
– 64ms, 8192-cycle refresh (commercial and
industrial)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
Options
• Configurations
– 128 Meg x 4 (32 Meg x 4 x 4 banks)
– 64 Meg x 8 (16 Meg x 8 x 4 banks)
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
• Write recovery (
t
WR)
t
WR = 2 CLK
1
• Plastic package – OCPL
2
– 54-pin TSOP II (400 mil) (standard)
– 54-pin TSOP II (400 mil) Pb-free
• Timing – cycle time
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
• Self refresh
– Standard
– Low power
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
• Revision
Notes:
1. See technical note TN-48-05 on
Micron's Web site.
2. Off-center parting line.
3. Available on x4 and x8 only.
4. Contact Micron for availability.
Marking
128M4
64M8
32M16
A2
TG
P
-75
-7E
3
None
L
4
None
IT
:C
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
-7E
-75
-7E
-75
Clock
Frequency
143 MHz
133 MHz
133 MHz
100 MHz
Access Time
CL = 2
5.4ns
6ns
CL = 3
5.4ns
5.4ns
Setup Time
1.5ns
1.5ns
1.5ns
1.5ns
Hold Time
0.8ns
0.8ns
0.8ns
0.8ns
PDF: 09005aef809bf8f3
512Mb_sdr.pdf - Rev. R 05/15 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2000 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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