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MT41J256M8DA-125:K TR

Description
SDRAM - DDR3 存储器 IC 2Gb(256M x 8) 并联 800 MHz 13.75 ns 78-FBGA(8x10.5)
Categorysemiconductor    memory   
File Size3MB,215 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT41J256M8DA-125:K TR Overview

SDRAM - DDR3 存储器 IC 2Gb(256M x 8) 并联 800 MHz 13.75 ns 78-FBGA(8x10.5)

MT41J256M8DA-125:K TR Parametric

Parameter NameAttribute value
category
MakerMicron Technology
series-
PackageTape and Reel (TR)
memory typeVolatile
memory formatDRAM
technologySDRAM - DDR3
storage2Gb(256M x 8)
memory interfacein parallel
Write cycle time - words, pages-
Voltage - Power supply1.425V ~ 1.575V
Operating temperature0°C ~ 95°C(TC)
Installation typesurface mount type
Package/casing78-TFBGA
Supplier device packaging78-FBGA(8x10.5)
Clock frequency800 MHz
interview time13.75 ns
Basic product numberMT41J256M8
2Gb: x4, x8, x16 DDR3 SDRAM
Features
DDR3 SDRAM
MT41J512M4 – 64 Meg x 4 x 8 Banks
MT41J256M8 – 32 Meg x 8 x 8 Banks
MT41J128M16 – 16 Meg x 16 x 8 Banks
Features
V
DD
= V
DDQ
= 1.5V ±0.075V
1.5V center-terminated push/pull I/O
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS READ latency (CL)
Posted CAS additive latency (AL)
Programmable CAS WRITE latency (CWL) based on
t
CK
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
T
C
of 0°C to 95°C
– 64ms, 8192 cycle refresh at 0°C to 85°C
– 32ms, 8192 cycle refresh at 85°C to 95°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Write leveling
Multipurpose register
Output driver calibration
Options
1
• Configuration
– 512 Meg x 4
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 10.5mm) Rev. K
– 78-ball (8mm x 10.5mm) Rev. N
• FBGA package (Pb-free) – x16
– 96-ball (8mm x 14mm) Rev. K
– 96-ball (8mm x 14mm) Rev. N
• Timing – cycle time
– 938ps @ CL = 14 (DDR3-2133)
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C
T
C
+95°C)
– Industrial (–40°C
T
C
+95°C)
• Revision
Note:
Marking
512M4
256M8
128M16
DA
EF
JT
TW
-093
-107
-125
-15E
-187E
None
IT
:K / :N
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade
-093
1, 2, 3, 4
-107
1, 2, 3
-125
1, 2,
-15E
1,
-187E
Notes:
1.
2.
3.
4.
Data Rate (MT/s)
2133
1866
1600
1333
1066
Target
t
RCD-
t
RP-CL
14-14-14
13-13-13
11-11-11
9-9-9
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.13
13.91
13.75
13.5
13.1
13.13
13.91
13.75
13.5
13.1
13.13
13.91
13.75
13.5
13.1
Backward compatible to 1066, CL = 7 (-187E).
Backward compatible to 1333, CL = 9 (-15E).
Backward compatible to 1600, CL = 11 (-125).
Backward compatible to 1866, CL = 13 (-107).
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. S 02/16 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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