MT41K1G8SN-107:A TR datasheet, PDF

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MT41K1G8SN-107:A TR: DescriptionSDRAM - DDR3L 存储器 IC 8Gb（1G x 8）并联 78-FBGA（9x13.2）; Categorysemiconductor memory; File Size300KB，15 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT41K1G8SN-107:A TR Overview

SDRAM - DDR3L 存储器 IC 8Gb（1G x 8）并联 78-FBGA（9x13.2）

MT41K1G8SN-107:A TR Parametric

Parameter Name	Attribute value
category
Maker	Micron Technology
series	-
Package	Tape and Reel (TR)
memory type	Volatile
memory format	DRAM
technology	SDRAM - DDR3L
storage	8Gb（1G x 8）
memory interface	in parallel
Write cycle time - words, pages	-
Voltage - Power supply	1.283V ~ 1.45V
Operating temperature	0°C ~ 95°C（TC）
Installation type	surface mount type
Package/casing	78-TFBGA
Supplier device packaging	78-FBGA（9x13.2）
Clock frequency	933 MHz
interview time	20 ns
Basic product number	MT41K1G8

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8Gb: x4, x8 TwinDie DDR3L SDRAM

Description

TwinDie™ 1.35V DDR3L SDRAM

MT41K2G4 – 128 Meg x 4 x 8 Banks x 2 Ranks

MT41K1G8 – 64 Meg x 8 x 8 Banks x 2 Ranks

Description

The 8Gb (TwinDie™) DDR3L SDRAM (1.35V) uses

Micron’s 4Gb DDR3L SDRAM die (essentially two

ranks of the 4Gb DDR3L SDRAM). Refer to Micron’s

4Gb DDR3 SDRAM data sheet for the specifications

not included in this document. Specifications for base

part number MT41K1G4 correlate to TwinDie manu-

facturing part number MT41K2G4; specifications for

base part number MT41K512M8 correlate to TwinDie

manufacturing part number MT41K1G8.

Options

• Configuration

– 128 Meg x 4 x 8 banks x 2 ranks

– 64 Meg x 8 x 8 banks x 2 ranks

• 78-ball FBGA package (Pb-free)

– (9.5mm x 11.5mm x 1.2mm) Die

Rev :E

– (8mm x 10.5mm x 1.2mm) Die

Rev :N, P

• Timing – cycle time

– 1.071ns @ CL = 13 (DDR3L-1866)

– 1.25ns @ CL = 11 (DDR3L-1600)

– 1.5ns @ CL = 9 (DDR3L-1333)

• Self refresh

– Standard

• Operating temperature

– Commercial (0°C

≤

95°C)

– Industrial (-40°C

≤

95°C)

• Revision

Note:

1. CL = CAS (READ) latency.

Marking

2G4

1G8

TRF

RKB

-107

-125

-15E

None

:E/:N/:P

Features

• Uses 4Gb Micron die

• Two ranks (includes dual CS#, ODT, CKE, and ZQ

balls)

• Each rank has eight internal banks for concurrent

operation

• V

= V

DDQ

= 1.35V (1.283–1.45V); backward com-

patible to V

= V

DDQ

= 1.5V ±0.075V

• 1.35V center-terminated push/pull I/O

• JEDEC-standard ball-out

• Low-profile package

• T

of 0°C to 95°C

– 0°C to 85°C: 8192 refresh cycles in 64ms

– 85°C to 95°C: 8192 refresh cycles in 32ms

– Industrial temperature (IT) available (Rev. E)

Table 1: Key Timing Parameters

Speed Grade

-107

Data Rate (MT/s)

1866

1600

1333

Target

RCD-

RP-CL

13-13-13

11-11-11

9-9-9

RCD

(ns)

CL (ns)

13.91

13.75

13.5

13.91

13.75

13.5

13.91

13.75

13.5

-125

-15E

Notes:

1. Backward compatible to 1333, CL = 9 (-15E).

2. Backward compatible to 1600, CL = 11 (-125).

CCMTD-1725822587-9746

DDR3L_8Gb_x4_x8_2CS_TwinDie_V90B.pdf - Rev. K 8/18 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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