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MT48LC4M16A2P-7E:J TR

Description
SDRAM 存储器 IC 64Mb(4M x 16) 并联 133 MHz 5.4 ns 54-TSOP II
Categorysemiconductor    memory   
File Size4MB,85 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT48LC4M16A2P-7E:J TR Overview

SDRAM 存储器 IC 64Mb(4M x 16) 并联 133 MHz 5.4 ns 54-TSOP II

MT48LC4M16A2P-7E:J TR Parametric

Parameter NameAttribute value
category
MakerMicron Technology
series-
PackageTape and Reel (TR)
memory typeVolatile
memory formatDRAM
technologySDRAM
storage64Mb(4M x 16)
memory interfacein parallel
Write cycle time - words, pages14ns
Voltage - Power supply3V ~ 3.6V
Operating temperature0°C ~ 70°C(TA)
Installation typesurface mount type
Package/casing54-TSOP (0.400", 10.16mm wide)
Supplier device packaging54-TSOP II
Clock frequency133 MHz
interview time5.4 ns
Basic product numberMT48LC4M16A2
128Mb: x4, x8, x16 SDRAM
Features
SDR SDRAM
MT48LC32M4A2 – 8 Meg x 4 x 4 Banks
MT48LC16M8A2 – 4 Meg x 8 x 4 Banks
MT48LC8M16A2 – 2 Meg x 16 x 4 Banks
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths (BL): 1, 2, 4, 8, or full
page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh modes: Standard and low power
(not available on AT devices)
• Auto Refresh
– 64ms, 4096-cycle refresh (commercial and
industrial)
– 16ms, 4096-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• Plastic package – OCPL
2
– 54-pin TSOP II (400 mil)
– 54-pin TSOP II (400 mil) Pb-free
– 60-ball TFBGA (8mm x 16mm)
– 60-ball TFBGA (8mm x 16mm) Pb-
free
– 54-ball VFBGA (x16 only) (8mm x
8mm)
– 54-ball VFBGA (x16 only) (8mm x
8mm) Pb-free
• Timing – cycle time
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
– 6.0ns @ CL = 3 (x16 only)
• Self refresh
– Standard
– Low power
• Revision
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)
Notes:
1. Contact Micron for availability.
2. Off-center parting line.
3. Only available on Revision G.
Options
Marking
TG
P
FB
1
BB
1
F4
B4
-75
3
-7E
-6A
None
L
3
:G/:L
None
IT
AT
1
Options
• Configurations
– 32 Meg x 4 (8 Meg x 4 x 4 banks)
1
– 16 Meg x 8 (4 Meg x 8 x 4 banks)
– 8 Meg x 16 (2 Meg x 16 x 4 banks)
• Write recovery (
t
WR)
t
WR = 2 CLK
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
-6A
-75
-7E
Clock
Frequency (MHz)
167
133
133
Marking
32M4
16M8
8M16
A2
Target
t
RCD-
t
RP-CL
3-3-3
3-3-3
2-2-2
t
RCD
(ns)
t
RP
(ns)
CL (ns)
18
20
15
18
20
15
18
20
15
PDF: 09005aef8091e66d
128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
1999 Micron Technology, Inc. All rights reserved.
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