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74LVCH16244ADGVJ

Description
缓冲器,非反向 4 元件 4 位每元件 三态 Output 48-TSSOP
Categorylogic    Logic - buffer, drives, receiver, transceiver   
File Size241KB,13 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
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74LVCH16244ADGVJ Overview

缓冲器,非反向 4 元件 4 位每元件 三态 Output 48-TSSOP

74LVCH16244ADGVJ Parametric

Parameter NameAttribute value
category
MakerNexperia
series74LVCH
Package卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带
logical typeBuffer, non-inverting
Number of components4
Number of digits per component4
input type-
Output typeThree states
Current - Output High, Low24mA,24mA
Voltage - Power supply1.2V ~ 3.6V
Operating temperature-40°C ~ 125°C(TA)
Installation typesurface mount type
Package/casing48-TFSOP (0.173", 4.40mm wide)
Supplier device packaging48-TSSOP
Basic product number74LVCH16244
74LVC16244A; 74LVCH16244A
Rev. 16 — 21 September 2021
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Product data sheet
1. General description
The 74LVC16244A; 74LVCH16244A is a 16-bit buffer/line driver with 3-state outputs. The device
can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four
output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on
nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either
3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V
and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input
rise and fall times. This device is fully specified for partial power down applications using I
OFF
. The
I
OFF
circuitry disables the output, preventing the potentially damaging backflow current through the
device when it is powered down.
The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up resistors to
hold unused inputs.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
5 V tolerant inputs/outputs for interfacing with 5 V logic
I
OFF
circuitry provides partial Power-down mode operation
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground bounce
Direct interface with TTL levels
High-impedance when V
CC
= 0 V
All data inputs have bus hold. (74LVCH16244A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C

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