a
FEATURES
Up to Nine Measurement Channels
Inputs Programmable-to-Measure Analog Voltage, Fan
Speed or External Temperature
External Temperature Measurement with Remote
Diode (Two Channels)
On-Chip Temperature Sensor
Five Digital Inputs for VID Bits
LDCM Support
System Management Bus (SMBus)
Chassis Intrusion Detect
Interrupt and Over Temperature Outputs
Programmable
RESET
Input Pin
Shutdown Mode to Minimize Power Consumption
Limit Comparison of all Monitored Values
System Hardware Monitor with
Remote Diode Thermal Sensing
ADM1024
APPLICATIONS
Network Servers and Personal Computers
Microprocessor-Based Office Equipment
Test Equipment and Measuring Instruments
PRODUCT DESCRIPTION
The ADM1024 is a complete system hardware monitor for
microprocessor-based systems, providing measurement and limit
comparison of various system parameters. Eight measurement
inputs are provided, of which three are dedicated to monitoring
5 V and 12 V power supplies and the processor core voltage.
The ADM1024 can monitor a fourth power-supply voltage by
measuring its own V
CC
. One input (two pins) is dedicated to a
remote temperature-sensing diode. Two further pins can be
(continued
on page 7)
FUNCTIONAL BLOCK DIAGRAM
V
CC
VID0/IRQ0
VID1/IRQ1
VID2/IRQ2
VID3/IRQ3
VID0–3 AND
FAN DIVISOR
REGISTER
ADM1024
NTEST OUT/ADD
SERIAL BUS
INTERFACE
SDA
SCL
100k½
PULLUPS
VID4/IRQ4
VID4 AND
DEVICE ID
REGISTER
FAN SPEED
COUNTER
ADDRESS
POINTER
REGISTER
CHANNEL
MODE
REGISTER
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
INTERRUPT
STATUS
REGISTERS
INT
MASK
REGISTERS
INTERRUPT
MASKING
CONFIGURATION
REGISTERS
CI
FAN1/AIN1
FAN2/AIN2
+V
CCP1
+2.5V
IN
/D2+
+5V
IN
+12V
IN
V
CCP2
/D2–
D1+
D1–
POWER TO CHIP
V
CC
BANDGAP
TEMPERATURE
SENSOR
INPUT
ATTENUATORS
AND
ANALOG
MULTIPLEXER
TEMPERATURE
CONFIGURATION
REGISTER
V
CC
100k½
V
CC
100k½
THERM
INT
10-BIT ADC
2.5V
BANDGAP
REFERENCE
ANALOG
OUTPUT
REGISTER AND
8-BIT DAC
CHASSIS
INTRUSION
CLEAR
REGISTER
V
CC
100k½
NTEST IN/AOUT
RESET
GND
REVISION HISTORY
REV. A
02/08—Rev 1: Conversion to ON Semiconductor
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
©2008 SCILLC. All rights reserved.
of patents or other rights of third parties
use, nor for any infringements
which
2008 - Rev.
from its use. No license is granted by implication or
February
may result
1
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Publication Order Number:
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
ADM1024/D
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADM1024–SPECIFICATIONS
Parameter
POWER SUPPLY
Supply Voltage, V
CC
Supply Current, I
CC
1, 2
(T
A
= T
MIN
to T
MAX
, V
CC
= V
MIN
to V
MAX
, unless otherwise noted)
Typ
3.30
1.4
1.0
45
Max
5.5
3.5
145
±
3
±
2
±
5
150
9
Unit
V
mA
mA
µA
°C
°C
°C
°C
°C
°C
µA
µA
Test Conditions/Comments
Min
2.8
Interface Inactive, ADC Active
ADC Inactive, DAC Active
Shutdown Mode
0°C
≤
T
A
≤
100°C
T
A
= 25°C
0°C
≤
T
A
≤
100°C
25°C
High Level
Low Level
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor Accuracy
Resolution
External Diode Sensor Accuracy
Resolution
Remote Sensor Source Current
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error, TUE (12 V
IN
)
TUE (AIN, V
CCP
, 2.5 V
IN
, 5 V
IN
)
Differential Nonlinearity, DNL
Power Supply Sensitivity
Conversion Time (Analog Input or Int. Temp)
Conversion Time (External Temperature)
Input Resistance (2.5 V, 5 V, 12 V, V
CCP1
, V
CCP2
)
Input Resistance (AIN1, AIN2)
ANALOG OUTPUT
Output Voltage Range
Total Unadjusted Error, TUE
Full-Scale Error
Zero-Scale Error
Differential Nonlinearity, DNL
Integral Nonlinearity
Output Source Current
Output Sink Current
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
Full-Scale Count
FAN1 and FAN2 Nominal Input RPM
5
80
4
±
1
±
3
±
1
110
6.5
80
±
1
754.8
9.6
140
5
±
4
±
3
±
1
856.8
200
%
%
LSB
%/V
µs
ms
kΩ
MΩ
V
%
%
LSB
LSB
LSB
mA
mA
%
rpm
rpm
rpm
rpm
kHz
V
V
(See Note 3)
0°C
≤
T
A
≤
100°C
4
(See Note 4)
0
±
1
2
±
1
2
1
2.5
±
3
±
5
±
1
I
L
= 2 mA
No Load
Monotonic by Design
±
12
255
8800
4400
2200
1100
22.5
0°C
≤
T
A
≤
100°C
Divisor = 1, Fan Count = 153
Divisor = 2, Fan Count = 153
Divisor = 3, Fan Count = 153
Divisor = 4, Fan Count = 153
0°C
≤
T
A
≤
100°C
I
OUT
= +3.0 mA, V
CC
= 2.85 V – 3.60 V
I
OUT
= –3.0 mA, V
CC
= 2.85 V – 3.60 V
(See Note 6)
Internal Clock Frequency
DIGITAL OUTPUTS NTEST_OUT
Output High Voltage, V
OH
Output Low Voltage, V
OL
OPEN-DRAIN DIGITAL OUTPUTS
(INT,
THERM, RESET)
Output Low Voltage, V
OL
High Level Output Current, I
OH
RESET
and CI Pulsewidth
OPEN-DRAIN SERIAL DATA BUS OUTPUT
(SDA)
Output Low Voltage, V
OL
High Level Output Current, I
OH
19.8
2.4
25.2
0.4
20
0.1
45
0.4
100
V
µA
ms
I
OUT
= –3.0 mA, V
CC
= 3.60 V
V
OUT
= V
CC
0.1
0.4
100
V
µA
I
OUT
= –3.0 mA, V
CC
= 2.85 V – 3.60 V
V
OUT
= V
CC
Rev. 1 | Page 2 of 28 | www.onsemi.com
–2–
REV. A
ADM1024
Parameter
SERIAL BUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
Glitch Immunity
DIGITAL INPUT LOGIC LEVELS
(ADD, CI,
RESET,
VID0–VID4, FAN1, FAN2)
Input High Voltage, V
IH
Input Low Voltage, V
IL
NTEST_IN
Input High Voltage, V
IH
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
SERIAL BUS TIMING
8
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
Start Setup Time, t
SU;STA
Start Hold Time, t
HD;STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
r
SCL, SDA Fall Time, t
f
Data Setup Time, t
SU;DAT
Data Hold Time, t
HD;DAT
Min
Typ
Max
Unit
Test Conditions/Comments
2.2
0.8
500
100
V
V
mV
ns
(See Note 7)
2.2
0.8
2.2
–1
1
20
400
50
1.3
600
600
1.3
0.6
100
V
V
V
µA
µA
pF
kHz
ns
µs
ns
ns
µs
µs
ns
µs
ns
ns
V
CC
= 2.85 V – 5.5 V
V
CC
= 2.85 V – 5.5 V
V
CC
= 2.85 V – 5.5 V
V
IN
= V
CC
V
IN
= 0
300
300
900
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
NOTES
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Typicals are at T
A
= 25°C and represent most likely parametric norm. Shutdown current typ is measured with V
CC
= 3.3 V.
3
TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators, including an external series input
protection resistor value between zero and 1 kΩ.
4
Total monitoring cycle time is nominally
m
×
755
µs
+
n
×
33244
µs,
where
m
is the number of channels configured as analog inputs, plus two for the internal V
CC
measurement and internal temperature sensor, and
n
is the number of channels configured as external temperature channels (D1 and D2).
5
The total fan count is based on two pulses per revolution of the fan tachometer output.
6
Open-drain digital outputs may have an external pull-up resistor connected to a voltage lower or higher than V
CC
(up to 6.5 V absolute maximum).
7
All logic inputs except ADD are tolerant of 5 V logic levels, even if V
CC
is less than 5 V. ADD is a three-state input that may connected to V
CC
, GND, or left open-circuit.
8
Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.2 V for a rising edge.
Specifications subject to change without notice.
t
R
t
LOW
SCL
t
F
t
HD:STA
t
HD:STA
SDA
t
HD:DAT
t
HIGH
t
SU:DAT
t
SU:STA
t
SU:STO
P
t
BUF
S
S
P
Figure 1. Diagram for Serial Bus Timing
Rev. 1 | Page 3 of 28 | www.onsemi.com
REV. A
–3–
ADM1024
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
NTEST OUT/ADD
THERM
SDA
SCL
FAN1/AIN1
FAN2/AIN2
CI
GND
V
CC
1
2
3
4
5
6
24
23
22
21
Positive Supply Voltage (V
CC
) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage on 12 V V
IN
Pin . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Voltage on AOUT, N TEST_OUT ADD, 2.5 V
IN
/D2+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
CC
+ 0.3 V)
Voltage on Any Other Input or Output Pin . . –0.3 V to +6.5 V
Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . .
±
5 mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
Maximum Junction Temperature (T
J
max) . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared 15 sec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200°C
ESD Rating All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
*Stresses
above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
VID0/IRQ0
VID1/IRQ1
VID2/IRQ2
VID3/IRQ3
VID4/IRQ4
19
+V
CCP1
TOP VIEW
(Not to Scale)
18
+2.5V
IN
/D2+
7
8
9
17
16
15
14
13
ADM1024
20
V
CCP2
/D2–
+5V
IN
+12V
IN
D1+
D1–
INT
10
NTEST IN/AOUT
11
RESET
12
THERMAL CHARACTERISTICS
24-Lead Small Outline Package:
θ
JA
= 50°C/W,
θ
JC
= 10°C/W.
ORDERING GUIDE
Model
ADM1024ARU
Temperature
Range
0°C to 100°C
Package
Description
24-Lead TSSOP
Package
Option
RU-24
Rev. 1 | Page 4 of 28 | www.onsemi.com
–4–
REV. A
ADM1024
PIN FUNCTION DESCRIPTIONS
Pin
No.
1
2
3
4
5
6
7
Mnemonic
NTEST_OUT/ADD
THERM
SDA
SCL
FAN1/AIN1
FAN2/AIN2
CI
Description
Digital I/O. Dual Function pin. This is a three-state input that controls the 2 LSBs of the Serial
Bus Address. This pin functions as an output when doing a NAND test.
Digital I/O. Dual Function pin. This pin functions as an interrupt output for temperature interrupts
only, or as an interrupt input for fan control. It has an on-chip 100 kΩ pull-up resistor.
Digital I/O. Serial Bus bidirectional Data. Open-drain output.
Digital Input. Serial Bus Clock.
Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to V
CC
) amplitude fan
tachometer input.
Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to V
CC
) amplitude fan
tachometer input.
Digital I/O. An active high input from an external latch which captures a Chassis Intrusion event.
This line can go high without any clamping action, regardless of the powered state of the ADM1024. The
ADM1024 provides an internal open drain on this line, controlled by Bit 6 of Register 40h or Bit 7 of
Register 46h, to provide a minimum 20 ms pulse on this line, to reset the external Chassis Intrusion Latch.
System Ground.
POWER (2.8 V to 5.5 V). Typically powered from 3.3 V power rail. Bypass with the parallel combination of
10
µF
(electrolytic or tantalum) and 0.1
µF
(ceramic) bypass capacitors.
Digital Output. Interrupt Request (open-drain). The output is enabled when Bit 1 of Register 40h
is set to 1. The default state is disabled. It has an on-chip 100 kΩ pull-up resistor.
Digital Input/Analog Output. An active-high input that enables NAND Test mode board-level connectivity
testing. Refer to section on NAND testing. Also functions as a programmable analog output when NAND
Test is not selected.
Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 45 ms minimum pulsewidth.
Set using Bit 4 in Register 40h. Also acts as reset input when pulled low (e.g., power-on reset). It has an
on-chip 100 kΩ pull-up resistor.
Analog Input. Connected to cathode of first external temperature sensing diode.
Analog Input. Connected to anode of first external temperature sensing diode.
Programmable Analog Input. Monitors 12 V supply.
Analog Input. Monitors 5 V supply.
Programmable Analog Input. Monitors second processor core voltage or cathode of second external
temperature sensing diode.
Programmable Analog Input. Monitors 2.5 V supply or anode of second external temperature sensing diode.
Analog Input. Monitors 1st processor core voltage (0 V to 3.6 V).
Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID4 Status Regis-
ter. Can also be reconfigured as an interrupt input. It has an on-chip 100 kΩ pull-up resistor.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 S tatus
Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 kΩ pull-up resistor.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0-VID3 Status
Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 kΩ pull-up resistor.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status
Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 kΩ pull-up resistor.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status
Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 kΩ pull-up resistor.
8
9
10
11
GND
V
CC
INT
NTEST_IN/AOUT
12
RESET
13
14
15
16
17
18
19
20
21
22
23
24
D1–
D1+
+12 V
IN
+5 V
IN
V
CCP2
/D2–
+2.5 V
IN
/D2+
+V
CCP1
VID4/IRQ4
VID3/IRQ3
VID2/IRQ2
VID1/IRQ1
VID0/IRQ0
Rev. 1 | Page 5 of 28 | www.onsemi.com
REV. A
–5–
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